XCCACE128-I Xilinx Inc, XCCACE128-I Datasheet - Page 36

• Manufacturer Part Number: XCCACE128-I
• Description: IC 128MBIT ACE FLASH CARD
• Manufacturer: Xilinx Inc

Specifications of XCCACE128-I

• Memory Size: 128Mb
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

System ACE CompactFlash Solution
Table 23: System ACE CF Controller Boundary-Scan Instructions
Boundary-Scan Register
The Boundary-Scan register, which is the primary test data register, is used to control and observe the state of device pins
during EXTEST and SAMPLE/PRELOAD instructions. For more information on the System ACE Boundary-Scan register
(such as bit sequence, 3-state control, and so forth), refer to the System ACE Boundary-Scan Description Language (BSDL)
file available from the software download area at:
Bit Sequence
The bit sequence of the device is obtainable from the Boundary-Scan Description Language (BSDL) Files. These files are
available from the software download area at:
Identification Register
The Identification Register known as the IDCODE is a fixed, vendor-assigned value that is used to electronically identify the
type of device and the manufacturer for a specific device being tested. The System ACE CF controller IDCODE register is
32 bits wide. The contents of this register can be shifted out for examination by selecting the IDCODE instruction. The
IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format,
described in
Table 24: System ACE CF Controller Identification Register
Bypass Register
The last standard 1149.1 Boundary-Scan data register in the System ACE CF controller is the single flip-flop BYPASS
register. It directly passes data serially from the TDI pin to the TDO pin during a bypass instruction. This register is initialized
to zero when the TAP controller is in the UPDATE-DR state.
TAP Timing Characteristics
IEEE 1149.1 boundary-scan (JTAG) testing is performed via the standard 4-wire Test Access Port (TAP). The Boundary
Scan timing waveforms and switching characteristics of the TAP are described in
36
BYPASS
SAMPLE/PRELOAD
IDCODE
EXTEST
Boundary-Scan Instruction
Version
0000
Table
TSTTMS
TSTTDI
TSTTCK
TSTTDO
24.
0ns
Figure 17: Test JTAG Boundary-Scan Port Timing Waveforms
0000001
Family
TTCKTDO
Binary Code [7:0]
11111111
00000001
00001001
00000000
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50ns
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TTAPTCK
TTAPTCK
Array Size
00000000
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TTCKTAP
TTCKTAP
VALID
.
Enables BYPASS
Enables boundary-scan SAMPLE/PRELOAD Operation
Enables shifting out 32-bit IDCODE
Enables boundary-scan EXTEST operation
.
100ns
Manufacturer
00001001001
Figure 17
150ns
Description
and
Required by IEEE 1149.1
DS080_46_030801
DS080 (v2.0) October 1, 2008
Table
Product Specification
25, respectively.
2
1
R