XCCACE128-I Xilinx Inc, XCCACE128-I Datasheet - Page 65

• Manufacturer Part Number: XCCACE128-I
• Description: IC 128MBIT ACE FLASH CARD
• Manufacturer: Xilinx Inc

Specifications of XCCACE128-I

• Memory Size: 128Mb
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 38: System ACE CF Controller Pin Table (IN = input, OUT2 = 2-State Output, OUT3 = 3-State Output)
DS080 (v2.0) October 1, 2008
Product Specification
CFGMODEPIN
CFGADDR0
CFGADDR1
CFGADDR2
Pin Name
CFGTDO
CFGTMS
CFRSVD
CFGTCK
TSTTMS
TSTTDO
CFGINIT
CFWAIT
TSTTCK
CFGTDI
CFREG
TSTTDI
CFCD1
CFCD2
CFWE
CFOE
R
Pin #
131
123
140
133
103
102
101
13
86
87
88
89
98
97
82
81
80
85
78
3
I/O Type
OUT2
OUT2
OUT2
OUT3
OUT3
OUT2
OUT3
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
I/O Supply Rail
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CCH
CCH
CCH
CCH
CCH
CCH
CCH
CCH
CCH
CCH
CCH
CCL
CCL
CCL
CCL
CCL
CCL
CCL
CCL
CCL
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Ext. Pull-up
Ext. Pull-up
Ext. Pull-up
Int. Pull-down
Int. Pull-down
Int. Pull-down
Termination
Ext. Pull-up
Int. Pull-up
Int. Pull-up
Int. Pull-up
Int. Pull-up
Int. Pull-up
Int. Pull-up
Int. Pull-up
N/A
N/A
N/A
N/A
N/A
N/A
(1)
(1)
(1)
CompactFlash
this pin is always driven to a 1 but is provided here
for future compatibility.
CompactFlash
CompactFlash
CompactFlash
LOW)
This pin must be pulled up to V
external pull-up resistor.
CompactFlash
CompactFlash
Configuration address select pin 0
Configuration address select pin 1
Configuration address select pin 2
Configuration mode pin:
• When 0, this pin instructs the System ACE CF
• When 1, this pin instructs the System ACE CF
Test JTAG port test data input
Test JTAG port test clock
Test JTAG port test data output
Configuration JTAG test data output
Configuration JTAG test data input
Configuration JTAG test clock
Configuration JTAG test mode select
Configuration JTAG INIT pin (active LOW); this pin
is used to sense when all devices are ready to be
programmed (i.e., INIT = 1 indicates target
device(s) are ready to receive configuration data
and INIT = 0 indicates that the target device(s) are
being cleared and are not ready to be configured)
Test JTAG port test mode select
controller to start the configuration process
when the CFGSTART bit is set in the
CONTROLREG register in the MPU interface.
controller to start the configuration process
immediately following reset.
System ACE CompactFlash Solution
register select line (active LOW);
write enable line (active LOW)
output enable line (active LOW)
memory cycle wait flag (active
card detect line 1 (active LOW)
card detect line 2 (active LOW)
Description
CCH
using an
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