XCCACE128-I Xilinx Inc, XCCACE128-I Datasheet - Page 37

• Manufacturer Part Number: XCCACE128-I
• Description: IC 128MBIT ACE FLASH CARD
• Manufacturer: Xilinx Inc

Specifications of XCCACE128-I

• Memory Size: 128Mb
• Memory Type: FLASH
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 25: System ACE CF Controller TAP Characteristics
Configuration JTAG Interface (CFGJTAG)
Configuration JTAG Port is the interface between the System ACE CF controller and the target FPGA chain. This port is
accessed when configuring the target FPGA chain of devices via any of the System ACE CF controller interfaces (Test
JTAG, MPU, or CompactFlash). To program or test the FPGA target chain, the data from these interfaces is converted to
IEEE 1149.1 Boundary-Scan (JTAG) serial data.
Typical Configuration Modes
The four System ACE CF controller interfaces are designed to work together in a number of different combinations. This
section discusses typical user configuration modes. A handful of signals determine which interface provides the
configuration data source.
determine which interface will be used. This is especially important when using multiple interfaces in a design, or when not
using the default values of these signals. The default values of these signals set the CompactFlash interface as the source
of configuration data.
Table 26: Configuration Signals Used for Selecting Configuration Modes and Active Design
Table 27: Active Configuration Modes
DS080 (v2.0) October 1, 2008
Product Specification
Notes:
1.
2.
3.
T
T
T
F
CFGMODE
CFGADDR[2:0]
CFGSEL
CFGSTART
CFGRESET
FORCECFGADDR
FORCECFGMODE
CompactFlash
CompactFlash
Microprocessor
Microprocessor
Test JTAG
Configuration Signal
(TAPTCK)
(TCKTAP)
(TCKTDO)
(TSTTCK)
The FORCECFGMODE bit in the CONTROLREG register of the MPU interface can be used to force the CFGMODE register bit to
override the System ACE CF controller CFGMODEPIN.
An X entry indicates “don’t care”.
The Test JTAG configuration mode is active regardless of the pin settings as long as none of the other configuration modes are in
operation.
Symbol
(Configure using the TSTJTAG port)
R
(Configure from CF immediately after CFGRESET)
(Configure from CF after receiving MPU start signal)
(Configure from MPU)
(Configure from MPU after receiving MPU start signal)
Configuration Interface
TSTTMS and TSTTDI setup time before rising edge of TSTTCK
TSTTMS and TSTTDI hold times after TSTTCK
TSTTCK falling edges to TSTTDO output valid
Maximum TSTTCK clock frequency
Table 26
Pin or MPU register bit
Pins or MPU register bits
MPU register bit
MPU register bit
MPU register bit (CFGRESET is a subset of the RESET pin)
MPU register bit (Overrides value on CFGADDR [2:0] pins)
MPU register bit (Overrides value on CFGMODEPIN)
describes these important signals, and
(3)
Parameter
Description
www.xilinx.com
CFGMODE
X
1
0
1
1
Table 27
(1)
System ACE CompactFlash Solution
CFGSEL
shows how they work together to
X
0
0
1
1
CFGMODE Register Bit = 0
Min
4
4
CFGMODEPIN = 1
CFGSTART
X
X
X
1
1
(2)
Default
Max
16.7
16
0
0
0
0
0
0
CFGRESET
Units
MHz
X
0
0
0
0
ns
ns
ns
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