C8051T610DB24 Silicon Laboratories Inc, C8051T610DB24 Datasheet - Page 73

Manufacturer Part Number

C8051T610DB24

Description

DAUGHTER BOARD T610 24QFN SOCKET

Manufacturer

Silicon Laboratories Inc

Datasheet

1.C8051T610DB32.pdf (218 pages)

Module/board Type

Socket Module - QFN

Processor To Be Evaluated

C8051T61x

Interface Type

USB

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

For Use With/related Products

C8051T610DK

Lead Free Status / RoHS Status

Lead free / RoHS Compliant, Lead free / RoHS Compliant

Other names

336-1507

C8051T610/1/2/3/4/5/6/7

Notes on Registers, Operands and Addressing Modes:

Rn - Register R0–R7 of the currently selected register bank.

@Ri - Data RAM location addressed indirectly through R0 or R1.

rel - 8-bit, signed (twos complement) offset relative to the first byte of the following instruction. Used by

SJMP and all conditional jumps.

direct - 8-bit internal data location’s address. This could be a direct-access Data RAM location (0x00–

0x7F) or an SFR (0x80–0xFF).

#data - 8-bit constant

#data16 - 16-bit constant

bit - Direct-accessed bit in Data RAM or SFR

addr11 - 11-bit destination address used by ACALL and AJMP. The destination must be within the same

2 kB page of program memory as the first byte of the following instruction.

addr16 - 16-bit destination address used by LCALL and LJMP. The destination may be anywhere within

the 8 kB program memory space.

There is one unused opcode (0xA5) that performs the same function as NOP.

Rev 1.0