C8051T610DB28 Silicon Laboratories Inc, C8051T610DB28 Datasheet - Page 104
![DAUGHTER BOARD T610 28QFN SOCKET](/photos/9/3/90367/c8051t610db28_sml.jpg)
C8051T610DB28
Manufacturer Part Number
C8051T610DB28
Description
DAUGHTER BOARD T610 28QFN SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T610DB32.pdf
(218 pages)
Specifications of C8051T610DB28
Module/board Type
Socket Module - QFN
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1506
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- Download datasheet (2Mb)
C8051T610/1/2/3/4/5/6/7
19.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
19.6. PCA Watchdog Timer Reset
The programmable watchdog timer (WDT) function of the programmable counter array (PCA) can be used
to prevent software from running out of control during a system malfunction. The PCA WDT function can
be enabled or disabled by software as described in Section “26.4. Watchdog Timer Mode” on page 200;
the WDT is enabled and clocked by SYSCLK/12 following any reset. If a system malfunction prevents user
software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The
state of the RST pin is unaffected by this reset.
19.7. EPROM Error Reset
If an EPROM read or write targets an illegal address, a system reset is generated. This may occur due to
any of the following:
The MEMERR bit (RSTSRC.6) is set following an EPROM error reset. The state of the RST pin is unaf-
fected by this reset.
19.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.
104
Programming hardware attempts to write or read an EPROM location which is above the user code
space address limit.
An EPROM read from firmware is attempted above user code space. This occurs when a MOVC
operation is attempted above the user code space address limit.
A Program read is attempted above user code space. This occurs when user code attempts to branch
to an address above the user code space address limit.
Rev 1.0
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