C8051T610DB28 Silicon Laboratories Inc, C8051T610DB28 Datasheet - Page 157
![DAUGHTER BOARD T610 28QFN SOCKET](/photos/9/3/90367/c8051t610db28_sml.jpg)
C8051T610DB28
Manufacturer Part Number
C8051T610DB28
Description
DAUGHTER BOARD T610 28QFN SOCKET
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T610DB32.pdf
(218 pages)
Specifications of C8051T610DB28
Module/board Type
Socket Module - QFN
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610DK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
336-1506
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24. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SYSCLK
Clock Divide
SPI0CKR
SFR Bus
SPI0DAT
Logic
Write
Transmit Data Buffer
Receive Data Buffer
Figure 24.1. SPI Block Diagram
7
6
Shift Register
5
SPI CONTROL LOGIC
4
3
Data Path
2
SFR Bus
SPI0CFG
Control
SPI0DAT
1
SPI0DAT
Read
0
Rev 1.0
Tx Data
Rx Data
C8051T610/1/2/3/4/5/6/7
Pin Interface
Control
Control
Logic
Pin
SPI0CN
MOSI
MISO
SCK
NSS
C
R
O
S
S
B
A
R
SPI IRQ
Port I/O
157
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