ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 199
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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18.3.2
18.3.3
SYNCCTRL - Synchronisation Control/Status Register
INTCTRL - Interrupt Control Register
• Bit 0 - ENABLE: RTC Enable
Setting this bit enables the RTC. The synchronization time between the RTC and the System
Clock domains is one half RTC clock cycle from writing the register and until this has effect in
RTC clock domain, i.e until the RTC starts.
For the RTC to start running the PER Register must also be set to a different value that zero.
• Bits 7:5 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 4- SYNCCNT: Enable Synchronization of the CNT register
Setting this bit will start synchronization of CNT register from the RTC clock to the System Clock
domain. The bit is automatically cleared when synchronization is done.
• Bits 3:1 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 - SYNCBUSY: RTC Synchronization Busy Flag
This flag is set when the CTRL or CNT registers are busy synchronizing from the System Clock
to the RTC clock domain. The CTRL register synchronization is triggered when it is written. The
CNT register are synchronized when the most significant byte of the register is written.
• Bits 7:4 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 3:2 - COMPINTLVL[1:0]: RTC Compare Match Interrupt Enable
These bits enable the RTC Compare Match Interrupt and select the interrupt level as described
in
enabled interrupt will trigger when the COMPIF in the INTFLAGS register is set.
Bit
+0x01
Read/Write
Reset Value
Bit
+0x02
Read/Write
Reset Value
Section 12. ”Interrupts and Programmable Multi-level Interrupt Controller” on page
7
-
R
0
7
-
R
0
6
-
R
0
6
-
R
0
5
-
R
0
5
-
R
0
SYNCCNT
R/W
4
0
4
-
R
0
COMPINTLVL[1:0]
R/W
3
3
-
R
0
0
R/W
2
2
-
R
0
0
R/W
1
1
-
R
0
0
OCINTLVL[1:0]
SYNCBUSY
R/W
R/W
0
0
0
0
SYNCCTRL
INTCTRL
123. The
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