ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 98
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ATAVRDISPLAYX
Manufacturer Part Number
ATAVRDISPLAYX
Description
KIT EVAL XMEGA DISPLAY
Manufacturer
Atmel
Specifications of ATAVRDISPLAYX
Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Silicon Manufacturer
Atmel
Silicon Family Name
ATxmega
Kit Contents
Board
Features
Temperature Sensor, Mono Speaker Via Audio Amplifier
Svhc
No SVHC (15-Dec-2010)
Core Architecture
AVR
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATAVRDISPLAYX
Manufacturer:
Atmel
Quantity:
135
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8.6
8.6.1
8077H–AVR–12/09
Register Description – Power Reduction
PRGEN - General Power Reduction Register
Table 8-2.
• Bit 1 - SEN: Sleep Enable
This bit must be set to make the MCU enter the selected sleep mode when the SLEEP instruc-
tion is executed. To avoid unintentional entering of sleep modes, it is recommended to write
SEN just before executing the SLEEP instruction, and clearing it immediately after waking up.
• Bit 7:5 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 4 - AES: AES Module
Setting this bit stops the clock to the AES module. When the bit is cleared the peripheral should
be reinitialized to ensure proper operation.
• Bit 3 - EBI: External Bus Interface
Setting this bit stops the clock to the External Bus Interface. When the bit is cleared the periph-
eral should be reinitialized to ensure proper operation. Note that the EBI is not present for all
devices.
• Bit 2 - RTC: Real-Time Counter
Setting this stops the clock to the Real Time Counter. When the bit is cleared the peripheral
should be reinitialized to ensure proper operation.
• Bit 1 - EVSYS: Event System
Setting this stops the clock to the Event System. When the bit is cleared the module will continue
like before the shutdown.
• Bit 0 - DMA: DMA Controller
Setting this stops the clock to the DMA Controller. This bit can only be set if the DMA Controller
is disabled.
Bit
+0x00
Read/Write
Initial Value
SMODE[2:0]
101
110
111
R
7
0
-
Sleep mode
R
6
0
-
SEN
1
1
1
R
5
0
-
AES
R/W
4
0
Group Configuration
ESTDBY
R/W
STDBY
EBI
3
0
-
RTC
R/W
2
0
EVSYS
R/W
Description
Reserved
Standby Mode
Extended Standby Mode
1
0
XMEGA A
DMA
R/W
0
0
PRGEN
98
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