CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 10

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

1.8. Switching Characteristics — Intel
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
Notes: 1. Certain timing parameters are normalized to the DSP clock, DCLKP, in nanoseconds. DCLKP =
10
Address setup before CS and RD low or CS and WR low
Address hold time after CS and RD low or CS and WR low
Delay between RD then CS low or CS then RD low
Data valid after CS and RD low
CS and RD low for read
Data hold time after CS or RD high
Data high-Z after CS or RD high
CS or RD high to CS and RD low for next read
CS or RD high to CS and WR low for next write
Delay between WR then CS low or CS then WR low
Data setup before CS or WR high
CS and WR low for write
Data hold after CS or WR high
CS or WR high to CS and RD low for next read
CS or WR high to CS and WR low for next write
2. This specification is characterized but not production tested. A 470 ohm pull-up resistor was used for
3. See T
1/DCLK. The DSP clock can be defined as follows:
External CLKIN Mode:
DCLK == CLKIN/4 before and during boot
DCLK == CLKIN after boot
Internal Clock Mode:
DCLK == 10MHz before and during boot, i.e. DCLKP == 100ns
DCLK == 65 MHz after boot, i.e. DCLKP == 15.4ns
It should be noted that DCLK for the internal clock mode is application specific. The application code
users guide should be checked to confirm DCLK for the particular application.
characterization to minimize the effects of external bus capacitance.
idd
from Intel Host Mode in
Parameter
Table 6 on page 46
(Note 3)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
®
Host Mode
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
iwpw
irdtw
icdw
idhw
iwtrd
irpw
idsu
icdr
idhr
idis
iwd
ias
iah
idd
ird
L
= 20 pF)
2*DCLKP + 10
2*DCLKP + 10
2*DCLKP + 10
2*DCLKP + 10
DCLKP + 10
DCLKP + 10
CS49300 Family DSP
Min
20
5
5
0
5
0
5
-
-
Max
21
22
∞
∞
-
-
-
-
-
-
-
-
-
-
-
DS339F7
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns