CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 40

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

3) After each byte (including the address and
4) The host should then clock data into the device
40
preceding any write. The 0x00 byte represents
the 7 bit of address (0000000b) and the
read/write bit set to 0 to designate a write.
each data byte) the host must release the data
line and provide a ninth clock for the CS493XX
to acknowledge. The CS493XX will drive the
data line low during the ninth clock to
acknowledge. If for some reason the CS493XX
does not acknowledge, it means that the last
byte sent was not received and should be
resent. If the resent byte fails to produce an
acknowledge, a stop condition should be sent
and the device should be reset.
Figure 22. I
WRITE ADDRESS BYTE
WHILE SCCLK IS HIGH
WHILE SCCLK IS HIGH
SET TO 0 FOR WRITE
RAISE SCDIO HIGH
DROP SCDIO LOW
SEND I
SEND DATABYTE
WITH MODE BIT
MORE DATA?
I
GET ACK
GET ACK
2
C STOP:
2
C
2
C START:
®
Write Flow Diagram
N
Y
5) At the end of a data transfer a stop condition
6.1.2.2. Reading in I
A read operation is necessary when the CS493XX
signals that it has data to be read. It does this by
dropping its interrupt request line (INTREQ) low.
When reading from the device in I
protocol will be used whether reading a single byte
or multiple bytes. The examples shown in this
document can be expanded to fit any read
situation.
sequence
1) An I
2) The host responds by sending an I
3) The start condition is followed by a 7-bit
4) After the falling edge of the serial control clock
5) The data is ready to be clocked out on the
most significant bit first, one byte at a time. The
CS493XX will (and must) acknowledge each
byte that it receives which means that after
each
acknowledge clock pulse on SCCLK and
release the data line, SCDIO.
must be sent. The stop condition is defined as
the rising edge of SCDIO while SCCLK is high.
CS493XX dropping INTREQ, signaling that it
has data to be read.
condition which is SCDIO dropping while
SCCLK is held high.
address and the read/write bit set high for a
read. The address for the CS493XX defaults to
0000000b. It is necessary to clock this address
in prior to any transfer in order for the
CS493XX to acknowledge the read. In other
words a byte of 0x01 should be clocked into the
device preceding any read. The 0x01 byte
represents the 7 bit address 0000000b and a
read/write bit set to 1 to designate a read.
(SCCLK) for the read/write bit of the address
byte, an acknowledge must be read in by the
host. The CS493XX will drive SCDIO low to
acknowledge the address byte and to indicate
that it is ready for a read operation. If an
acknowledge is not sent by the CS493XX, a
stop condition should be issued and the read
sequence should be restarted.
SCDIO line at this point. Data clocked out by
2
C
Figure 23
®
byte
read transaction is initiated by the
CS49300 Family DSP
the
shows a typical I
host
2
C
®
must
2
C
provide
®
, the same
2
2
C
DS339F7
C
®
®
read
start
an