CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 66

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

The flow diagram given in Figure 36 demonstrates
the interaction required by the microcontroller
during autoboot. After placing the decoder into a
reset state, the host selects the page in memory
containing first code by driving uC15 to a low state.
The host also drives ABOOT low and holds it in a
low state until the rising edge of RESET to initiate
autoboot. As noted in the autoboot section, the
ABOOT pin should be connected to an open-drain
output of the microcontroller so as to allow the
specified pull-up resistor to generate the high
value. The open-drain driver is required because
the DSP will begin using the pin as an output after
a successful download (INTREQ and ABOOT are
multiplexed on the same pin).
After waiting for 175 ms, the download should have
completed. During the wait period, the host should
ignore all INTREQ behavior (mask the INTREQ
66
Figure 41. Example Contents of a Paged 32 Kilo-
bytes External Memory (Total 256 Kilobytes)
0x0FFFF
0x1FFFF
0x2FFFF
0x3FFFF
0x07FFF
0x17FFF
0x27FFF
0x37FFF
0x00000
0x08000
0x10000
0x18000
0x20000
0x28000
0x30000
0x38000
Address line uC15, uC16, and
DTS-ES Extended Surround
MPEG Multichannel with
Virtual Dolby Digital with
Pro Logic II with Cirrus
uC17 used for paging
VMAx VirtualTheater
Dolby Digital with
Extra Surround
DTS-ES Neo:6
Pro Logic II
LOGIC7
HDCD
MP3
interrupt). The host can then verify that the code
has successfully initialized itself by reading a
variable from the application and checking the
returned value against the default value. Any
variable can be used for the verification step, but a
robust design will select a variable whose value is
neither all 0’s nor all 1’s. If the first read attempt
returns an incorrect value, a 5 ms wait should be
inserted and the read should be repeated. If a
second invalid number is read, the entire boot
process should be repeated. When the number
returned matches the default value for the variable
read, the host knows that the application is
resident in the DSP and awaiting further
instruction. Please see Section 8.2, “Autoboot” on
page 57 for more information.
For systems that would prefer to store all
application codes in an external parallel Flash
Memory (vs. a OTP EPROM) in order to realize a
“field-upgradable”
[e-mail] for information
about how to control the GPIO pins of the DSP via
messaging to the SPI or I
8.8. CDB49300-MEMA.0
The CDB49300-MEMA.0 is an external memory
adapter
CDB4923/CDB4930 REV-A.0 Evaluation Board.
The schematic for the CDB49300-MEMA.0 is
shown in Figure 42. This board is an example of
one possible external memory configuration.
In addition to autobooting from external EPROM,
certain application codes require real-time access
to external SRAM, such as decoding of AAC
Multichannel streams, which have a 5.1 channel
output. These applications require that the DSP
has real-time access to 70nS (or faster) 32
Kilobyte SRAM. The 128 Kilobyte SRAM on the
CDB49300-MEMA.0 is made accessible by the
DSP when the host drives uC18 high. The external
256 Kilobyte EPROM is accessible to the DSP
when the host controller drives uC18 low. The with
uC15, uC16, and uC17 lines are used to page
between the various code images.
card
designed
CS49300 Family DSP
system,
2
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