CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 70

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

10.2. Digital Audio Input Port
The digital audio input port, or DAI, is used for both
compressed and PCM digital audio data input. In
addition this port supports a special clocking mode
in which a clock can be input to directly drive the
internal 33 bit counter.
Input Port,” on page 70
mnemonics and pin numbers associated with the
DAI.
The DAI is fully configurable including support for
I
addition the DAI can be programmed for slave
clocks, where LRCLKN1 and SCLKN1 are inputs,
or master clocks, where LRCLKN1 and SCLKN1
are outputs. In order for clocks to be master, the
internal PLL must be used.
STCCLK2 can also be programmed to drive the
internal 33 bit counter. This counter would typically
be driven by a 90kHz clock. The internal counter is
used by certain application code for audio/video
synchronization purposes.
10.3. Compressed Data Input Port
The compressed data input port, or CDI, can be
used for both compressed and PCM data input.
Table 14
number of the pins associated with the CDI port on
the CS493XX.
70
SDATAN1
STCCLK2
SCLKN1
LRCLKN1
2
SDATA
LRCLK
S, left justified and multichannel formats. In
Pin Name
SCLK
shows the mnemonic, pin name and pin
Table 13. Digital Audio Input Port
MSB
Per Channel
M Clocks
Secondary STC clock
Pin Description
Serial Bit Clock
Serial Data In
LSB
Frame Clock
MSB
Table 13, “Digital Audio
Per Channel
shows the pin names,
M Clocks
LSB
Figure 45. Multichannel Format
MSB
Pin Number
Per Channel
M Clocks
22
25
26
LSB
The CDI is fully configurable including support for
I
can also be programmed for slave clocks, where
LRCLKN2 and SCLKN2 are inputs, or master
clocks, where LRCLKN2 and SCLKN2 are outputs.
In order for clocks to be mastered, the internal PLL
must be used.
In addition the CDI can be configured for bursty
compressed data input. Bursty audio delivery is a
special format in which only clock (CMPCLK) and
data (CMPDAT) are used to deliver compressed
data to the CS493XX (i.e. no frame clock or
LRCLK). A third line, CMPREQ, is used to request
more data from the host. It is an indicator that the
CS493XX internal FIFO is low on data and can
accept another burst. Typically this mode is used
for compressed data delivery where asynchronous
data transfer occurs in the system, i.e. in a system
such as a set-top box or HDTV. PCM data can not
be presented in this mode since data is interpreted
as a continuous stream with no word boundaries.
10.4. Byte Wide Digital Audio Data Input
Two types of byte wide parallel delivery are
supported by the CS493XX. If using one of the
parallel control modes described in
“Parallel Host Communication” on page
the parallel interface can also be used for
SDATAN2
CMPDATA
SCLKN2
CMPCLK
LRCLKN2
CMPREQ
2
MSB
Pin Name
S, left justified and multichannel formats. The CDI
Per Channel
M Clocks
Table 14. Compressed Data Input Port
LSB
MSB
Compressed Data In
Data Request Out
Pin Description
Per Channel
Serial Bit Clock
CS49300 Family DSP
M Clocks
Serial Data In
Frame Clock
LSB
MSB
Per Channel
M Clocks
Pin Number
Section 6.2,
LSB
DS339F7
44, then
27
28
29
MSB