CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 3

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

LIST OF FIGURES
DS339F7
9. HARDWARE CONFIGURATION ................................................................................... 68
10.DIGITAL INPUT & OUTPUT ........................................................................................... 69
11.HARDWARE CONFIGURATION ................................................................................... 74
12.PIN DESCRIPTIONS ....................................................................................................... 82
13.ORDERING INFORMATION ........................................................................................... 87
14.PACKAGE DIMENSIONS .............................................................................................. 88
15.DOCUMENT REVISIONS
Figure 1. RESET Timing ........................................................................................................ 9
Figure 2. CLKIN with CLKSEL = VSS = PLL Enable ............................................................. 9
Figure 3. Intel
Figure 4. Intel
Figure 5. Motorola
Figure 6. Motorola
Figure 7. SPI Control Port Timing ........................................................................................ 15
Figure 8. I2C
Figure 9. Digital Audio Input Data, Master and Slave Clock Timing ..................................... 19
Figure 10. Serial Compressed Data Timing ......................................................................... 20
Figure 11. Parallel Data Timing (when not in a parallel control mode) ................................. 21
Figure 12. Digital Audio Output Data, Input and Output Clock Timing ................................. 23
Figure 13. I
Figure 14. I
Figure 15. SPI Control .......................................................................................................... 31
Figure 16. SPI Control with External Memory ...................................................................... 32
Figure 17. Intel
8.4 Internal Boot ............................................................................................................. 63
8.5 Application Failure Boot Message ............................................................................ 63
8.6 Resetting the CS493XX ............................................................................................ 63
8.7 External Memory Examples ...................................................................................... 64
8.8 CDB49300-MEMA.0 ................................................................................................. 66
10.1 Digital Audio Formats .............................................................................................. 69
10.2 Digital Audio Input Port ........................................................................................... 70
10.3 Compressed Data Input Port ................................................................................... 70
10.4 Byte Wide Digital Audio Data Input ......................................................................... 70
10.5 Digital Audio Output Port ......................................................................................... 72
11.1 Address Checking ................................................................................................... 74
11.2 Input Data Hardware Configuration ........................................................................ 74
11.3 Output Data Hardware Configuration ...................................................................... 78
11.4 Creating Hardware Configuration Messages .......................................................... 80
8.7.1 Non-Paged Autoboot Memory ...................................................................... 64
8.7.2 32 Kilobyte Paged Autoboot Memory ........................................................... 65
10.1.1 I
10.1.2 Left Justified ............................................................................................... 69
10.1.3 Multichannel ............................................................................................... 69
10.4.1 Parallel Delivery with Parallel Control ........................................................ 71
10.4.2 Parallel Delivery with Serial Control ........................................................... 71
10.5.1 IEC60958 Output ........................................................................................ 73
11.2.1
11.3.1 Output Configuration Considerations ........................................................ 80
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C
C
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Control Port Timing ...................................................................................... 17
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Parallel Host Mode Read Cycle .................................................................. 11
Parallel Host Mode Write Cycle .................................................................. 11
Control ........................................................................................................ 29
Control with External Memory ..................................................................... 30
2
Parallel Control Mode ................................................................................ 33
S .............................................................................................................. 69
Input Configuration Considerations ......................................................... 77
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Parallel Host Mode Read Cycle ........................................................... 13
Parallel Host Mode Write Cycle ........................................................... 13
............................................................................................ 89
CS49300 Family DSP
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