CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 47

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

The flow diagram shown in
sequence of events that define a one-byte read in
Intel mode. The protocol presented in
will now be described in detail.
1) The host must first drive the A1 and A0 register
2) The host now indicates that the selected
3) Once the data is valid, the host can read the
4) The host should now terminate the read cycle
6.2.2. Motorola Parallel Host
The Motorola parallel host communication mode is
implemented using the pins given in
INTREQ pin is controlled by the application code
when a parallel host communication mode has
been selected. When the code supports INTREQ
notification, the INTREQ pin is asserted whenever
the DSP has an outgoing message for the host.
DS339F7
Figure 25. Intel Mode, One-Byte Read Flow Dia-
address pins of the CS493XX with the address
of the desired Parallel I/O Register. Note that
only the Host Message register and the Host
Control register can be read.
Host Message: A[1:0]==00b.
Host Control:
register will be read. The host initiates a read
cycle by driving the CS and RD pins low.
value of the selected register from the
DATA[7:0] pins of the CS493XX.
by driving the CS and RD pins high.
Communication Mode
ADDRESS A PARALLEL I/O REGISTER
(A[1:0] SET APPROPRIATELY
READ BYTE FROM
RD (HIGH)
DATA [7:0]
CS (HIGH)
CS (LOW)
RD (LOW)
A[1:0]==01b.
Figure 25
illustrates the
Table
Figure 25
7. The
This same information is reflected by the
HOUTRDY bit of the Host Control Register (A[1:0]
= 01b).
INTREQ is useful for informing the host of
unsolicited messages. An unsolicited message is
defined as a message generated by the DSP
without
Unsolicited messages can be used to notify the
host of conditions such as a change in the
incoming audio data type (e.g. PCM --> AC-3)
6.2.2.1. Writing a Byte in Motorola Mode
Information provided in this section is intended as
a functional description of how to write control
information to the CS493XX. The system designer
must insure that all of the timing constraints of the
Motorola Parallel Host Mode Write Cycle are met.
The flow diagram shown in
sequence of events that define a one-byte write in
Motorola mode. The protocol presented in
Figure 26
1) The host must drive the A1 and A0 register
Chip Select
Data Strobe
Read or Write Select
Register Address Bit 1
Register Address Bit 0
Interrupt Request
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Table 7. Motorola Mode Communication Signals
address pins of the CS493XX with the address
of the address of the desired Parallel I/O
Register.
Host Message:
Host Control:
PCMDATA:
Mnemonic
an
will now be described in detail.
associated
CS49300 Family DSP
CS
DS
INTREQ
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
R/W
A1
A0
Pin Name
Figure 26
host
read
A[1:0]==00b.
A[1:0]==01b.
A[1:0]==10b.
18
4
5
6
7
19
8
9
10
11
14
15
16
17
illustrates the
Pin Number
request.
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