CDB42528 Cirrus Logic Inc, CDB42528 Datasheet - Page 79

• Manufacturer Part Number: CDB42528
• Description: BOARD EVAL FOR CS42528/CS49300
• Manufacturer: Cirrus Logic Inc

Specifications of CDB42528

• Main Purpose: Audio, Audio Processing
• Embedded: Yes, DSP
• Utilized Ic / Part: CS49300, CS42528
• Primary Attributes: 8 Single-Ended Analog Inputs and Outputs, 4 S/PDIF Inputs and 2 S/PDIF Outputs
• Secondary Attributes: Parallel, RS422, RS232, UDSP Interfaces
• Product: Audio Modules
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1503

DS339F7
22
24
3
32
34
B Value
Table 23. Output Data Format Configuration
Multichannel (2 channel)
20-bit Left Justified
(SCLK must be at least 128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
covered in AN162 and AN163)
Multichannel (4 channel)
20-bit Left Justified
(SCLK must be at least 128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
covered in AN162 and AN163)
Multichannel (6 channel)
24-bit Left Justified
(SCLK must be at least 256Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
covered in AN162 and AN163)
Multichannel (2 channel)
24-bit Left Justified
(SCLK must be at least 128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
covered in AN162 and AN163)
Multichannel (4 channel)
24-bit Left Justified
(SCLK must be at least 128Fs
for this mode)
(Configuration of AUDATA3 as S/PDIF
(IEC60958) or Digital Audio in the
format of I
covered in AN162 and AN163)
AUDATA0, 1, 2 (or AUDATA0
for Multichannel Modes)
(Parameter B) (Continued)
DAO Data Format Of
2
2
2
2
2
S or Left Justified is
S or Left Justified is
S or Left Justified is
S or Left Justified is
S or Left Justified is
0x80027F
0xFC7FFF
0x80017F
0x018000
0x80027C
0xF01F00
0x80017C
0x001300
0x80027F
0xFC7FFF
0x80017F
0x010000
0x80027C
0xF01F00
0x80017C
0x001300
0x80027F
0xFC7FFF
0x80027C
0xF01F00
0x80027D
0xF01F00
0x80027E
0xF01F00
0x80027F
0xFC7FFF
0x80027C
0xF01F00
0x80017F
0x018000
0x80027F
0xFC7FFF
0x80017F
0x010000
0x80027C
0xF01F00
Message
Hex
0
(default)
1
2
3
0
(default)
1
2
0
(default)
1
E Value
C Value
D Value
Table 26. Output SCLK Polarity Configuration
Table 24. Output MCLK Configuration
Table 25. Output SCLK Configuration
Data Valid on Rising Edge
(clocked out on falling)
Data Valid on Falling Edge
(clocked out on rising)
256Fs
512Fs
128Fs
384Fs
(SCLK must be 64Fs in this
mode and MCLK must be an
input)
64Fs
128Fs
256Fs
MCLK Frequency
SCLK Frequency
SCLK Polarity
CS49300 Family DSP
(Parameter C)
(Parameter D)
(Parameter E)
0x80027F
0xF7FFFF
0x80017F
0x080000
0x80027F
0xFFE7FF
0x80027F
0xFFE7FF
0x80017F
0x001000
0x80027F
0xFFE7FF
0x80017F
0x001800
0x80027F
0xFFE7FF
0x80017F
0x000800
Message
Message
0x80027F
0xFFF8FF
0x80017F
0x000100
0x80027F
0xFFF8FF
0x80017F
0x000200
0x80027F
0xFFF8FF
0x80017F
0x000300
Message
Hex
Hex
Hex
79