EVB9221-MINI SMSC, EVB9221-MINI Datasheet
EVB9221-MINI
Specifications of EVB9221-MINI
Related parts for EVB9221-MINI
EVB9221-MINI Summary of contents
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... Reduced Power Modes — Numerous power management modes — Wake on LAN — Magic packet wakeup — Wakeup indicator event signal — Link Status Change SMSC LAN9221/LAN9221i LAN9221/LAN9221i High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Single chip Ethernet controller — ...
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... Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’ ...
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... Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.1 System Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.10.3 Internal PHY Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.11 Detailed Reset Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.11.1 Hardware Reset Input (nRESET 3.11.2 Resume Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.11.3 Soft Reset (SRST 3.11.4 PHY Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SMSC LAN9221/LAN9221i 3 DATASHEET Revision 2.7 (03-15-10) ...
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... RX and TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.1 RX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.2.2 TX FIFO Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.3 System Control and Status Registers 5.3.1 ID_REV—Chip ID and Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.3.2 IRQ_CFG—Interrupt Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 4 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 5.5.13 PHY Special Control/Status 127 Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.1 Equivalent Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.2 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 6.2.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 129 SMSC LAN9221/LAN9221i 5 DATASHEET Revision 2.7 (03-15-10) ...
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... Worst Case Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.6 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 7.7 Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Chapter 8 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 8.1 56-QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Chapter 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 6 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Figure 6.7 TX Data FIFO Direct PIO Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Figure 6.8 Power Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 6.9 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Figure 6.10 EEPROM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Figure 8.1 56 Pin QFN Package Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 8.2 56 Pin QFN Recommended PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SMSC LAN9221/LAN9221i 7 DATASHEET Revision 2.7 (03-15-10) ...
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... Table 7.6 I/O Buffer Characteristics VDDVARIO=3.3V +/- 300mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 7.7 I/O Buffer Characteristics VDDVARIO=2.5V +/- 10 145 Table 7.8 I/O Buffer Characteristics VDDVARIO=1.8V +/- 10 146 Table 7.9 100BASE-TX Transceiver Characteristics 147 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 8 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet Table 7.10 10BASE-T Transceiver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 7.11 LAN9221/LAN9221i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 8.1 56 Pin QFN Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Table 9.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 SMSC LAN9221/LAN9221i 9 DATASHEET Revision 2.7 (03-15-10) ...
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... Change”. This signal is ideal for triggering system power-up using remote Ethernet wakeup events. The device can be removed from the low power state via a host processor command. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 10 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... Block Diagram Microprocessor/ Microcontroller The SMSC LAN9221/LAN9221i integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9221/LAN9221i Ethernet MAC/PHY controller is designed and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus ...
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... Offload Engine 10/100 TX Status FIFO Ethernet RX Status FIFO MAC MIL - RX Elastic 2kB to 14kB Buffer - 128 bytes Configurable RX FIFO MIL - TX Elastic Buffer - 2K bytes Figure 1.2 Internal Block Diagram 12 DATASHEET Datasheet Figure 1.2, "Internal EEPROM (Optional) EEPROM Controller 10/100 Ethernet LAN PHY SMSC LAN9221/LAN9221i ...
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... Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9221/LAN9221i. An external PME (Power Management Event) interrupt is provided to indicate detection of a wakeup event. 1.10 General Purpose Timer The general-purpose timer has no dedicated function within the LAN9221/LAN9221i and may be programmed to issue a timed interrupt. SMSC LAN9221/LAN9221i 13 DATASHEET Revision 2.7 (03-15-10) ...
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... The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian processors and includes mixed endian support for FIFO accesses. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 14 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... XTAL1/CLKIN** 55 VDDVARIO 56 **DENOTES A MULTIFUNCTION PIN NOTE: When HP Auto-MDIX is activated, the TPO+/- pins can function as TPI+/- and vice-versa NOTE: Exposed pad (VSS) on bottom of package must be connected to ground Figure 2.1 56-QFN Pin Configuration (Top View) SMSC LAN9221/LAN9221i SMSC 56-QFN (TOP VIEW) VSS 15 DATASHEET D7 ...
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... Receive Positive Input (reversed Transmit Negative Output (normal) Receive Negative Input (reversed Receive Positive Input (normal) Transmit Positive Input (reversed Receive Negative Input (normal) Transmit Negative Output (reversed Must be connected to ground through a 12.4K ohm 1% resistor. 16 DATASHEET Datasheet DESCRIPTION DESCRIPTION SMSC LAN9221/LAN9221i ...
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... GPO3, TX_EN, TX_EN/TX_CLK TX_CLK EEPROM Chip EECS Select EEPROM Clock, EECLK/GPO4/ GPO4 RX_DV, RX_DV/RX_CLK RX_CLK SMSC LAN9221/LAN9221i BUFFER NUM TYPE PINS VIS/VO8 1 EEPROM Data: This bi-directional pin can be connected to a serial EEPROM DIO. This is optional. General Purpose Output 3: This pin can also ...
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... LAN9221/LAN9221i. The LAN9221/LAN9221iwill only wake up when it detects a host write cycle (assertion of nCS and nWR). Although any write to the LAN9221/LAN9221i, regardless of the data written, will wake-up the device when power-saving mode required that the BYTE_TEST register be used for this purpose. SMSC LAN9221/LAN9221i ...
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... Duplex Indicator ). Variable Voltage VDDVARIO I/O Power Common Ground VSS +3.3V Regulator VDD33REG Power Supply SMSC LAN9221/LAN9221i BUFFER NUM TYPE PINS VIS 1 Enables Auto-MDIX. Pull high or leave unconnected to enable Auto-MDIX, pull low to (PU) disable Auto-MDIX. Note: When operating at reduced VDDVARIO voltage levels (less than 3 ...
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... D0 D11 37 VDD18CORE VDDVARIO 38 EEDIO/GPO3 D10 39 EECS D9 40 EECLK/GPO4 D8 41 PME D7 42 nRESET EXPOSED PAD MUST BE CONNECTED TO VSS 20 DATASHEET Datasheet DESCRIPTION PIN NUM PIN NAME 43 IRQ 44 TPO- 45 TPO+ 46 VDD33A 47 TPI- 48 TPI+ 49 VDD33A 50 EXRES 51 VDD33A 52 AMDIX_EN 53 VDD18A 54 XTAL2 55 XTAL1/CLKIN 56 VDDVARIO SMSC LAN9221/LAN9221i ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Datasheet Table 2.6 External Pull-Up/Pull-Down Resistor Values I/O VOLTAGE 3.3V +/- 300mV 2.5 +/- 10% 1.8V +/- 10% SMSC LAN9221/LAN9221i PULL-UP/PULL-DOWN RESISTOR VALUE (OHMS) 10K 7.5K 4.7K 21 DATASHEET Revision 2.7 (03-15-10) ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 2.7 Buffer Types DESCRIPTION (Note 2.2) (Note 2.2) for additional information. and the individual signal descriptions in for more information. 22 DATASHEET Datasheet (Note 2.1) (Note 2.1) (Note 2.1) (Note 2.1) Section Section 2.2, Section SMSC LAN9221/LAN9221i ...
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... MAC through which all transmitted and received data and status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks reducing and minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. SMSC LAN9221/LAN9221i 23 DATASHEET Revision 2.7 (03-15-10) ...
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... This allows the packet to be received, and then processed by host software transmitted on the network. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 24 DATASHEET Datasheet Figure 3.1, SMSC LAN9221/LAN9221i ...
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... If the frame fails the filter, the Ethernet MAC function does not receive the packet. The host has the option of accepting or ignoring the packet. MCPAS PRMS INVFILT SMSC LAN9221/LAN9221i Figure 3.1 VLAN Frame for more information on this register. Table 3.1 Address Filtering Modes HO HPFILT ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O HO HPFILT DATASHEET Datasheet DESCRIPTION Hash Filtering for physical and multicast addresses Inverse Filtering Promiscuous Pass all multicast frames. Frames with physical addresses are perfect-filtered Pass all multicast frames. Frames with physical addresses are hash- filtered SMSC LAN9221/LAN9221i ...
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... When wake-up frame detection is enabled via the WUEN bit of the Control and Status the state of the Disable Broadcast Frame (BCAST) bit in the Register. SMSC LAN9221/LAN9221i Table 3.2, "Wake-Up Frame Filter Register Structure" Register, a broadcast wake-up frame will wake-up the device despite 27 DATASHEET Section 5.4.11, " ...
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... FILTER I BYTE MASK DESCRIPTION Table 3.4 FILTER i COMMANDS Table 3.5 describes the Filter i Offset bit fields. 28 DATASHEET Datasheet Filter 1 Reserved Filter 0 Command Command Filter 0 Offset Filter 0 CRC-16 Filter 2 CRC-16 shows the Filter I command register. SMSC LAN9221/LAN9221i ...
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... The device will also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame. SMSC LAN9221/LAN9221i Table 3.5 Filter i Offset Bit Definitions FILTER I OFFSET DESCRIPTION Table 3 ...
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... VLAN tag. This value is typically 8100h. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Frame Data Calculate Checksum Figure 3.4 RXCOE Checksum Calculation 30 DATASHEET Datasheet Figure 3. SMSC LAN9221/LAN9221i ...
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... Figure 3.6 Ethernet Frame with VLAN Tag {DSAP, SSAP, CTRL, OUI[23:16 DST SRC 1DWORD Figure 3.7 Ethernet Frame with Length Field and SNAP Header SMSC LAN9221/LAN9221i L3 Packet Calculate Checksum Figure 3.5 Type II Ethernet Frame L3 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum 31 DATASHEET ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O {OUI[15:0], PID[15:0 Packet Calculate Checksum {OUI[15:0], PID[15:0 Packet Calculate Checksum COE_CR—Checksum Offload Engine Control Register Register) and vice versa. These functions cannot be enabled 32 DATASHEET Datasheet Section 3.13.3) enables the SMSC LAN9221/LAN9221i ...
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... TX checksum preamble to include the partial checksum. The partial checksum can be replaced by the completed checksum calculation by setting the TXCSLOC pointer to point to the location of the partial checksum. SMSC LAN9221/LAN9221i COE_CR—Checksum Offload Engine Control Table 3.7). The TX checksum preamble instructs the TXCOE 3" ...
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... This is not a fatal error. The LAN9221/LAN9221i will reset its read counters and restart a new cycle on the next read. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3.7 TX Checksum Preamble DESCRIPTION 34 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... LAN9221/LAN9221i. Logically, the endian control logic is applied after the word swap logic for write operations, and before the word swap logic for read operations. SMSC LAN9221/LAN9221i 98. This register affects how words on the data bus Figure 3.2 ...
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... R X/TX D ata FIFO Port R X/TX D ata FIFO D irect A ccess (addresses 00h FIFO Port Endian O rdering D irect FIFO A ccess Endian Logic " P" Logic D [15:0] (H ost D ata B us) illustrates the byte ordering applied by the 36 DATASHEET Datasheet A ccess (FIFO _SEL = 1) FSELEN [28]) O rdering Logic SMSC LAN9221/LAN9221i ...
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... A[ A[ HOST DATA BUS SMSC LAN9221/LAN9221i WORD_SWAP != FFFF_FFFFh (FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) MSB LSB A[ A[ WORD_SWAP = FFFF_FFFFh (FPORTEND = 0 for Data FIFO port access on addresses 00h-3Ch) AND/OR (FSELEND = 0 for Data FIFO direct access when FIFO_SEL=1) ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O FIFO Access via Data Direct FIFO Access via FIFO Port (00h-3Ch) FIFO_SEL Host Data Bus Host Data Bus D[15:8] D[7:0] D[15: DATASHEET Datasheet CSR Access Host Data Bus D[7:0] D[15:8] D[7: SMSC LAN9221/LAN9221i ...
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... EPC_BSY bit is cleared. In all cases the host must wait for EPC_BSY to clear before modifying the E2P_CMD register. Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM the host must first issue the EWEN command. SMSC LAN9221/LAN9221i Section 5.3.23, "E2P_CMD – provides an explanation of the supported EEPROM 39 DATASHEET 111 ...
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... EEPROM Read Idle Write Data Register Write Command Register Read Command Register Section 5.3.23, "E2P_CMD – EEPROM Command Register," DATASHEET Datasheet Idle Write Command Register Read Command Register Busy Bit = 0 Read Data Register SMSC LAN9221/LAN9221i ...
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... ERAL (Erase All): If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM.The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT) 1 EEDIO (INPUT) SMSC LAN9221/LAN9221i Figure 3.5 EEPROM ERASE Cycle 0 0 ...
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... Erase/Write Enable command is issued. EECS EECLK EEDIO (OUTPUT) EEDIO (INPUT) Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I Figure 3.7 EEPROM EWDS Cycle Figure 3.8 EEPROM EWEN Cycle 42 DATASHEET Datasheet t CSL t CSL SMSC LAN9221/LAN9221i ...
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... E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not respond within 30ms. EECS EECLK EEDIO (OUTPUT EEDIO (INPUT) Table 3.9, "Required EECLK each EEPROM operation. SMSC LAN9221/LAN9221i Figure 3.9 EEPROM READ Cycle Figure 3 ...
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... D0 (Normal) state, when the READY bit is set, can the rest of the device be accessed. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3.9 Required EECLK Cycles REQUIRED EECLK CYCLES for a detailed description of these registers. for detailed EEPROM timing specifications. 44 DATASHEET Datasheet and Section 5.3.24, SMSC LAN9221/LAN9221i ...
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... If properly enabled via the ED_EN and PME_EN bits, the LAN9221/LAN9221i will assert the PME hardware signal upon detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b. SMSC LAN9221/LAN9221i Table 7.2, “Power Consumption Device and and Table 7.2, “Power Consumption Device and System 142, shows the power consumption values for each power state. Section 3.5, " ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3.10 Power Management States D0 D1 (WOL) Full ON Full ON Full ON RX Power Mgmt. Block On Full ON OFF Full ON Full ON KEY CLOCK ON BLOCK DISABLED – CLOCK ON FULL OFF 46 DATASHEET Datasheet D2 (ENERGY DETECT) Energy Detect Power-Down OFF OFF OFF SMSC LAN9221/LAN9221i ...
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... This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to 5.5.1, "Basic Control Register," on page 119 SMSC LAN9221/LAN9221i WOL_EN WUPS ED_EN ...
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... Section 5.5.11, "Interrupt Source Flag," on page Section 3.11.1, "Hardware Reset Input (nRESET)" for additional information. NASR REGISTERS Note 3.19 MIL MAC Note 3. DATASHEET Datasheet Section 126. If the EEPROM MAC ADDR. CONFIG. PHY RELOAD STRAPS Note 3.18 LATCHED SMSC LAN9221/LAN9221i ...
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... This self-clearing bit will return to ‘0’ at which time the PHY reset is complete. 3.12 TX Data Path Operation Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided among multiple buffers. Each buffer starts with a two DWORD TX command (TX command SMSC LAN9221/LAN9221i 49 DATASHEET Section 6.10, "Reset Revision 2.7 (03-15-10) ...
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... After writing the command, the host can then move the payload data into the TX FIFO. TX status DWORD’s are stored in the TX status FIFO to be read by the host at a later time upon completion of the data transmission onto the wire. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 50 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... LAN9221/LAN9221i in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation and other packet processing parameters are included in the command structure. The following diagram illustrates the buffer format. SMSC LAN9221/LAN9221i init Idle ...
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... Optional offset DWORD0 3rd . . . Optional offset DWORDn Offset + Data DWORD0 . . . . . Last Data & PAD Optional Pad DWORD0 . . . Optional Pad DWORDn Last Figure 3.14 TX Buffer Format Format", shows the TX Buffer written into the LAN9221/LAN9221i DATASHEET Datasheet 0 for a detailed explanation on SMSC LAN9221/LAN9221i ...
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... This cumulative value is compared against the Packet Length field in the TX command ‘B’ word and if they do not correlate, the TXE flag is set. Note: The buffer size specified does not include the buffer end alignment padding or data start offset added to a buffer. SMSC LAN9221/LAN9221i Table 3.12 TX Command 'A' Format DESCRIPTION [25] [24] ...
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... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 3.13 TX Command 'B' Format DESCRIPTION Register, the TX checksum offload engine (TXCOE) Table 3.14, "TX DATA Start Table 3.14 TX DATA Start Offset 11 10 D[31:24] D[23:16] 54 DATASHEET Datasheet Offset", shows the 01 00 D[15:8] D[7:0] SMSC LAN9221/LAN9221i ...
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... OR of bits 11, 10 this status word. 14:12 Reserved. These bits are reserved. Always write zeros to this field to guarantee future compatibility. 11 Loss of Carrier. When set, this bit indicates the loss of carrier during transmission. SMSC LAN9221/LAN9221i DESCRIPTION 55 DATASHEET Revision 2.7 (03-15-10) ...
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... Any DWORD-long data added as part of the End Padding is removed from each buffer before the data is written to the TX data FIFO. Any end padding that is less than 1 DWORD is passed to the TX data FIFO Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 56 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
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... End Alignment” Buffer 1: 0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data 16-Byte “Buffer End Alignment” SMSC LAN9221/LAN9221i 57 DATASHEET Revision 2.7 (03-15-10) ...
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... TX Command 'B' 10-Byte Data Start Offset 17-Byte Payload Data 5-Byte End Padding Figure 3.15 TX Example 1 58 DATASHEET Datasheet TX Data FIFO TX Command 'A' TX Command 'B' 79-Byte Payload TX Command 'A' 15-Byte Payload TX Command 'A' 17-Byte Payload NOTE: Extra bytes betw een buffers are not transmitted SMSC LAN9221/LAN9221i ...
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... Buffer End Alignment = 0 Data Start Offset = 6 First Segment = 1 Last Segment = 1 Buffer Size =183 TX Command 'B' Packet Length = 183 SMSC LAN9221/LAN9221i illustrates the TX command structure for this example, and also shows Data Written to the 0 TX Command 'A' TX Command 'B' 6-Byte Data Start Offset 183-Byte Payload Data 3B End Padding Figure 3 ...
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... COE_CR register. For more information, refer to Checksum Offload Engine Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O illustrates the TX command structure for this example, and also shows (TXCOE)". 60 DATASHEET Datasheet Section 3.6.2, "Transmit SMSC LAN9221/LAN9221i ...
Page 61
... Data Start Offset TX Command 'B' Packet Length = 115 TX Checksum Enable = 1 17-Byte Payload Data 5-Byte End Padding SMSC LAN9221/LAN9221i NOTE: When enabled, the TX Checksum transmitted. The FS bit in TX Command 'A', the 0 CK bit in TX Command 'B' and the TXCOE_EN bit in the COE_CR register must all be set for the TX checksum to be generated ...
Page 62
... It is possible to read multiple packets out of the RX data FIFO in one continuous stream. It should be noted that the programmed Offset and Padding will be added to each individual packet in the stream, since packet boundaries are maintained. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 62 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 63
... The host should perform the proper number of reads, as indicated by the packet length plus the start offset and the amount of optional padding added to the end of the frame, from the RX data FIFO. Last Packet Figure 3.18 Host Receive Routine Using Interrupts Figure 3.19 Host Receive Routine with Polling SMSC LAN9221/LAN9221i init Idle RX Interrupt Read RX ...
Page 64
... RX_DUMP bit, please refer to Register," on page 87. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Section 3.13.4, "Stopping and Starting the Receiver," on page Section 5.3.7, "RX_CFG—Receive Configuration 64 DATASHEET Datasheet 67. For more SMSC LAN9221/LAN9221i ...
Page 65
... RX Data FIFO. The RX checksum is enabled by setting the RXCOE_EN bit in the Control Register. For more information on the RX checksum, refer to Checksum Offload Engine SMSC LAN9221/LAN9221i Figure 3.20 assumed that the host has previously read the associated 31 Optional offset DWORD0 ...
Page 66
... Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 31 Order Optional offset DWORD0 1st . 2nd . Optional offset DWORDn ofs + First Data DWORD . . . . Last Data DWORD RX Checksum Optional Pad DWORD0 . . Optional Pad DWORDn Last DESCRIPTION 66 DATASHEET Datasheet 0 SMSC LAN9221/LAN9221i ...
Page 67
... If the Receiver Error (RXE) flag is asserted for any reason, the receiver will continue operation. RX Error (RXE) will be asserted under the following conditions: A host underrun of RX data FIFO A host underrun of the RX status FIFO An overrun of the RX status FIFO It is the duty of the host to identify and resolve any error conditions. SMSC LAN9221/LAN9221i DESCRIPTION 67 DATASHEET Revision 2.7 (03-15-10) ...
Page 68
... Encoder 125 Mbps Serial MLT-3 Tx MLT-3 MLT-3 Converter Driver MLT-3 CAT-5 MLT-3 Figure 4.1 100Base-TX Data Path Figure 4.1. Each major block is explained below. 68 DATASHEET Datasheet Scrambler 25MHz by 5 bits and PISO Magnetics Table 4.1. Each 4-bit data-nibble SMSC LAN9221/LAN9221i ...
Page 69
... INVALID, RX_ER if during RX_DV 00001 V INVALID, RX_ER if during RX_DV 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER if during RX_DV SMSC LAN9221/LAN9221i Table 4.1 4B/5B Code Table RECEIVER INTERPRETATION 0000 DATA 0001 0010 0011 0100 0101 0110 0111 ...
Page 70
... The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100Base-Tx Transmitter. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 4.1 4B/5B Code Table (continued) RECEIVER INTERPRETATION 70 DATASHEET Datasheet TRANSMITTER INTERPRETATION INVALID INVALID INVALID SMSC LAN9221/LAN9221i ...
Page 71
... This clock is used to extract the serial data from the received signal. 4.3.3 NRZI and MLT-3 Decoding The DSP generates the MLT-3 recovered levels that are fed to the MLT-3 converter. The MLT-3 is then converted to an NRZI data stream. SMSC LAN9221/LAN9221i 100M PLL 25MHz 4B/5B ...
Page 72
... The 4-bit wide data is sent to the TX10M block. The nibbles are converted to a 10Mbps serial NRZI data stream. The 10M PLL locks onto the external clock or internal oscillator and produces a 20MHz Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 72 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 73
... Auto-negotiation is a mechanism for exchanging configuration information between two link-partners and automatically selecting the highest performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28 of the IEEE 802.3 specification. SMSC LAN9221/LAN9221i 73 DATASHEET Revision 2.7 (03-15-10) ...
Page 74
... Any difference in the main content of the link code words at this time will cause auto-negotiation to re-start. Auto-negotiation will also re-start if not all of the required FLP bursts are received. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 74 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 75
... Format"). The CRS value, and subsequently the No Carrier value, are invalid during any full-duplex transmission. Therefore, these signals cannot be used as a verification method of transmitted packets when transmitting in 10/100 Mbps full-duplex modes. SMSC LAN9221/LAN9221i In this mode, If data is received while the PHY is 75 DATASHEET Section 3 ...
Page 76
... Receiving Half-Duplex Transmitting Half-Duplex Receiving Full-Duplex Transmitting Full-Duplex Receiving Half-Duplex Transmitting Half-Duplex Receiving Full-Duplex Transmitting Full-Duplex Receiving Figure 4.3, the SMSC LAN9221/LAN9221i Auto-MDIX 76 DATASHEET Datasheet CRS BEHAVIOR (Note 4.1) Active Active Low Active Active Active Low Active Active Active Low Active ...
Page 77
... The figure below shows the signal names at the RJ-45 connector, The mapping of these signals to the pins on the LAN9221/LAN9221i is as follows: TXP = TPO+ TXN = TPO- RXP = TPI+ RXN = TPI- Figure 4.3 Direct cable connection vs. Cross-over cable connection. SMSC LAN9221/LAN9221i 77 DATASHEET Revision 2.7 (03-15-10) ...
Page 78
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O RESERVED EEPROM Port MAC CSR Port TX Status FIFO PEEK TX Status FIFO Port RX Status FIFO PEEK RX Status FIFO Port TX Data FIFO Alias Ports TX Data FIFO Port RX Data FIFO Alias Ports RX Data FIFO Port Figure 5.1 Memory Map 78 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 79
... When the TX Status FIFO PEEK Port is read, the top of the TX Status FIFO is not popped. The TX data FIFO is Write Only aliased to 16 DWORD locations. The host may access the top of the TX Data FIFO through any of these locations. SMSC LAN9221/LAN9221i DESCRIPTION 79 DATASHEET ...
Page 80
... Automatic Flow Control Configuration EEPROM Command EEPROM Data Reserved for future use 80 DATASHEET Datasheet DEFAULT See Page 81. 00000000h 00000000h 00000000h - 87654321h 48000000h 00000000h 00000000h 00050000h 00000000h 00000000h 00001200h 00000000h 00000000h 0000FFFFh 0000FFFFh - 00000000h - 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - SMSC LAN9221/LAN9221i ...
Page 81
... IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the IRQ pin. When clear, the IRQ output is disabled and permanently deasserted. This bit has no effect on any internal interrupt status bits. 7-5 Reserved SMSC LAN9221/LAN9221i 50h Size: DESCRIPTION 54h Size: ...
Page 82
... When set, the IRQ output is a Push-Pull driver. When configured as an open-drain output the IRQ_POL field is ignored, and the interrupt output is always active low. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 82 DATASHEET Datasheet TYPE DEFAULT R/W 0 NASR RO - R/W 0 NASR SMSC LAN9221/LAN9221i ...
Page 83
... Section 3.13.5, "Receiver Errors," on page 67 description of the conditions that will cause an RXE. Transmitter Error (TXE). 13 transmitter has encountered an error. Please refer to "Transmitter Errors," on page will cause a TXE. SMSC LAN9221/LAN9221i 58h Size: DESCRIPTION his interrupt is issued when the receiver is T Generated when the TX Status ...
Page 84
... GPIO [2:0] (GPIOx_INT). Interrupts are generated from the GPIO’s. These interrupts are configured through the GPIO_CFG register. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 84 DATASHEET Datasheet TYPE DEFAULT RO - R/WC 0 R/WC 0 R/WC 0 R/ R/WC 0 R/WC 0 R/WC 000 SMSC LAN9221/LAN9221i ...
Page 85
... TX Status FIFO Full Interrupt (TSFF_INT_EN Status FIFO Level Interrupt (TSFL_INT_EN Dropped Frame Interrupt Enable (RXDF_INT_EN) 5 Reserved 4 RX Status FIFO Full Interrupt (RSFF_INT_EN Status FIFO Level Interrupt (RSFL_INT_EN) 2-0 GPIO [2:0] (GPIOx_INT_EN). SMSC LAN9221/LAN9221i 5Ch Size: DESCRIPTION 85 DATASHEET 32 bits TYPE DEFAULT R R/W ...
Page 86
... RX Status FIFO Level interrupt (RSFL) will be generated. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 64h Size: DESCRIPTION 68h Size: DESCRIPTION 86 DATASHEET Datasheet 32 bits TYPE DEFAULT RO 87654321h 32 bits TYPE DEFAULT R/W 48h R/W 00h RO - R/W 00h SMSC LAN9221/LAN9221i ...
Page 87
... Modifications to the upper bits will take affect on the next DWORD read. 7-0 Reserved [31] [30 SMSC LAN9221/LAN9221i 6Ch Size: DESCRIPTION for bit definitions Table 5.2 RX Alignment Bit Definitions End Alignment 4-byte alignment 16-byte alignment 32-byte alignment Reserved 87 DATASHEET 32 bits TYPE ...
Page 88
... All writes to this bit are ignored while this bit is high. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 70h Size: DESCRIPTION 88 DATASHEET Datasheet 32 bits TYPE DEFAULT R SMSC LAN9221/LAN9221i ...
Page 89
... TX_CLK running), the reset will not complete and the soft reset operation will timeout and this bit will be set to a ‘1’. The host processor must correct the problem and issue another soft reset. SMSC LAN9221/LAN9221i 74h Size: for details on stopping the transmitter and receiver ...
Page 90
... The LAN9221/LAN9221i must always be read at least once after power- up, reset, or upon return from a power-saving state or write operations will not function. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION 90 DATASHEET Datasheet TYPE DEFAULT SC 0 SMSC LAN9221/LAN9221i ...
Page 91
... SMSC LAN9221/LAN9221i Table 5.3 Valid TX/RX FIFO Allocations TX STATUS FIFO RX DATA FIFO SIZE (BYTES) 512 512 512 512 512 512 512 512 512 512 512 512 512 91 DATASHEET RX STATUS FIFO ...
Page 92
... Please refer to section “Receive Data FIFO Fast Forward” on page 64 for detailed information regarding the use of RX_FFWD. 30-0 Reserved Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 78h Size: DESCRIPTION 92 DATASHEET Datasheet 32 bits TYPE DEFAULT R SMSC LAN9221/LAN9221i ...
Page 93
... TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in DWORDS used in the TX Status FIFO. 15-0 TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes, available in the TX data FIFO. The application should never write more data than is available, as indicated by this value. SMSC LAN9221/LAN9221i 7Ch Size: DESCRIPTION 80h Size: ...
Page 94
... PME_POL field is ignored, and the output is always active low. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 84h Size: DESCRIPTION – These bits set the 94 DATASHEET Datasheet 32 bits TYPE DEFAULT 00b R R/W 0b NASR SMSC LAN9221/LAN9221i ...
Page 95
... Note: With the exception of HW_CFG and PMT_CTRL, read access to any internal resources is forbidden while the READY bit is cleared. Note: On power-up, this bit can be polled to indicate when a valid soft reset (SRST) can be performed. SMSC LAN9221/LAN9221i DESCRIPTION Figure 3.12 47. Section 3.10.2.3, "Power 47). ...
Page 96
... Reserved Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 88h Size: DESCRIPTION for the EEPROM Enable bit function definitions. 96 DATASHEET Datasheet 32 bits TYPE DEFAULT RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 000 RO - R/W 0000 RO - SMSC LAN9221/LAN9221i ...
Page 97
... Timer is put into the run state. When cleared, the GP Timer is halted. On the transition of this bit the GPT_LOAD field will be preset to FFFFh. 28-16 Reserved 15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded into the GP-Timer. SMSC LAN9221/LAN9221i DESCRIPTION Table 5.4 EEPROM Enable Bit Definitions EEDIO FUNCTION EEDIO GPO3 GPO3 ...
Page 98
... Endian Support" Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 90h Size: DESCRIPTION 98h Size: DESCRIPTION for more information. 98 DATASHEET Datasheet 32 bits TYPE DEFAULT FFFFh 32 bits TYPE DEFAULT R/W 00000000h NASR Section SMSC LAN9221/LAN9221i ...
Page 99
... BITS 31-0 RX Dropped Frame Counter (RX_DFC). This counter is incremented every time a receive frame is dropped. RX_DFC is cleared on any read of this register. An interrupt can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). SMSC LAN9221/LAN9221i 9Ch Size: DESCRIPTION A0h Size: DESCRIPTION ...
Page 100
... MAC CSR Data. Value read from or written to the MAC CSR’s. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O A4h Size: DESCRIPTION A8h Size: DESCRIPTION 100 DATASHEET Datasheet 32 bits TYPE DEFAULT R/W 00h 32 bits TYPE DEFAULT R/W 00000000h SMSC LAN9221/LAN9221i ...
Page 101
... Flow Control on Address Decode (FCADD). When this bit is set, the LAN9221/LAN9221i will assert back pressure when the AFC level is reached and a frame addressed to the LAN9221/LAN9221i is received. This field has no function in full-duplex mode. SMSC LAN9221/LAN9221i ACh Size: DESCRIPTION 101 DATASHEET ...
Page 102
... DATASHEET Datasheet TYPE DEFAULT R/W 0 10Mbs Mode 7.2uS 12.2uS 17.2uS 27.2uS 52.2uS 102.2uS 152.2uS 202.2uS 252.2uS 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS 602.2uS SMSC LAN9221/LAN9221i ...
Page 103
... Note: EPC busy will be high immediately following power-up or reset. After the EEPROM controller has finished reading (or attempting to read) the MAC address from the EEPROM the EPC Busy bit is cleared. SMSC LAN9221/LAN9221i B0h Size: DESCRIPTION 103 DATASHEET ...
Page 104
... Address Loaded” bit indicates a successful load of the MAC address. 27-10 Reserved. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION [28] OPERATION 0 0 READ 0 1 EWDS 1 0 EWEN 1 1 WRITE 0 0 WRAL 0 1 ERASE 1 0 ERAL 1 1 Reload 104 DATASHEET Datasheet TYPE DEFAULT R SMSC LAN9221/LAN9221i ...
Page 105
... This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial EEPROM. BITS 31-8 Reserved 7:0 EEPROM Data. Value read from or written to the EEPROM. SMSC LAN9221/LAN9221i DESCRIPTION When set, this bit indicates that a valid EEPROM B4h Size: DESCRIPTION 105 ...
Page 106
... Multicast Hash Table Low MII Access MII Data Flow Control VLAN1 Tag VLAN2 Tag Wake-up Frame Filter Wake-up Control and Status Checksum Offload Engine Control 106 DATASHEET Datasheet DEFAULT 00040000h 0000FFFFh FFFFFFFFh 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h SMSC LAN9221/LAN9221i ...
Page 107
... Pass Bad Frames (PASSBAD). When set, all incoming frames that passed address filtering are received, including runt frames and collided frames. 15 Hash Only Filtering mode (HO). When set, the address check Function operates in the Imperfect Address Filtering mode both for physical and multicast addresses 14 Reserved SMSC LAN9221/LAN9221i 1 Attribute: 00040000h Size: DESCRIPTION 107 ...
Page 108
... These functions cannot be enabled simultaneously. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O DESCRIPTION Register, a broadcast wake-up frame will wake-up the device despite the COE_CR—Checksum Offload Engine Control 108 DATASHEET Datasheet WUCSR—Wake-up Register) and vice versa. SMSC LAN9221/LAN9221i ...
Page 109
... Receiver Enable (RXEN). When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY. When reset, the MAC’s receiver is disabled and will not receive any frames from the internal PHY. 1-0 Reserved SMSC LAN9221/LAN9221i DESCRIPTION BOLMT Value # Bits Used from LFSR Counter 2’b00 2’ ...
Page 110
... The host can update the contents of this field after the initialization process has completed. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 2 Attribute: 0000FFFFh Size: Section 4.6 for more information on the EEPROM. Section DESCRIPTION 110 DATASHEET Datasheet R/W 32 bits 5.4.3 SMSC LAN9221/LAN9221i ...
Page 111
... EEPROM are also shown 0x78 Figure 5.2 Example ADDRL, ADDRH and EEPROM Setup Note: By convention, the left most byte of the Ethernet address (in this example 0x12) is the most significant byte and is transmitted/received first. SMSC LAN9221/LAN9221i 3 Attribute: FFFFFFFFh Size: Section 4.6 DESCRIPTION ADDRN ...
Page 112
... Lower 32 bits of the 64-bit Hash Table Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 4 Attribute: 00000000h Size: DESCRIPTION 5 Attribute: 00000000h Size: for further details. DESCRIPTION 112 DATASHEET Datasheet R/W 32 bits R/W 32 bits Table 5.4.4, SMSC LAN9221/LAN9221i ...
Page 113
... Register, or the read data from the PHY register whose index is specified in the MII Access Register. BITS 31-16 Reserved 15-0 MII Data. This contains the 16-bit value read from the PHY read operation or the 16-bit data value to be written to the PHY before an MII write operation. SMSC LAN9221/LAN9221i 6 Attribute: 00000000h Size: DESCRIPTION 7 ...
Page 114
... When writing this register the FCBSY bit must always be zero. Applications must always write a zero to this bit Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 8 Attribute: 00000000h Size: DESCRIPTION 114 DATASHEET Datasheet R/W 32 bits SMSC LAN9221/LAN9221i ...
Page 115
... VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If used, this register must be set to 0x8100. SMSC LAN9221/LAN9221i 9 Attribute: 00000000h ...
Page 116
... Magic Packet Enable (MPEN). When set, Magic Packet Wake-up mode is enabled. 0 Reserved Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O B Attribute: 00000000h Size: DESCRIPTION C Attribute: 00000000h Size: DESCRIPTION 116 DATASHEET Datasheet WO 32 bits R/W 32 bits SMSC LAN9221/LAN9221i ...
Page 117
... This bit may only be changed if the RX data path is disabled. 0: The RXCOE is bypassed 1: The RXCOE is enabled Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of the MAC_CR—MAC Control simultaneously. SMSC LAN9221/LAN9221i D Attribute: 00000000h Size: DESCRIPTION Register) and vice versa. These functions cannot be enabled 117 ...
Page 118
... Special Modes Register 27 Special Control/Status Indications 29 Interrupt Source Register 30 Interrupt Mask Register 31 PHY Special Control/Status Register Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Table 5.8, "LAN9221/LAN9221i PHY Control and Status 118 DATASHEET Datasheet Register". SMSC LAN9221/LAN9221i ...
Page 119
... Duplex Mode full duplex half duplex. Ignored if Auto Negotiation is enabled (0.12 = 1). 7 Collision Test enable COL test disable COL test 6-0 Reserved Note 5.1 The default value of this bit is determined by the auto-negotiation process. SMSC LAN9221/LAN9221i 0 Size: DESCRIPTION 119 DATASHEET 16-bits TYPE ...
Page 120
... PHY ID Number. Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier (OUI), respectively. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 1 Size: DESCRIPTION 2 Size: DESCRIPTION 120 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/ RO/LL 0 RO/ 16-bits TYPE DEFAULT RO 0x0007h SMSC LAN9221/LAN9221i ...
Page 121
... Selector Field. [00001] = IEEE 802.3 Note 5.2 When both symmetric PAUSE and asymmetric PAUSE support are advertised (value of 11), the device will only be configured to, at most, one of the two settings upon auto- negotiation completion. SMSC LAN9221/LAN9221i 3 Size: DESCRIPTION 4 Size: DESCRIPTION Note 5 ...
Page 122
... Selector Field. [00001] = IEEE 802.3 Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 5 Size: DESCRIPTION 122 DATASHEET Datasheet 16-bits TYPE DEFAULT 00001 SMSC LAN9221/LAN9221i ...
Page 123
... Reset to “1” by hardware reset, unaffected by SW reset. 0 Reserved. Write as “0”. Ignore on read. Note 5.3 The default value of this bit will vary dependant on the current link state of the line. SMSC LAN9221/LAN9221i 6 Size: DESCRIPTION 17 Size: DESCRIPTION ...
Page 124
... Table 5.9 MODE Control DEFAULT REGISTER BIT VALUES REGISTER 0 [13,12,10,8] 0000 0001 1000 1001 1100 1100 N/A X10X Note 5.4 124 DATASHEET Datasheet 16-bits TYPE DEFAULT RW, NASR RW, 111 NASR RW, 00001b NASR REGISTER 4 [8,7,6,5] N/A N/A N/A N/A 0100 0100 N/A 1111 SMSC LAN9221/LAN9221i ...
Page 125
... Receive PLL 10M is locked on the reference clock. In this mode 10M data packets cannot be received. 9-5 Reserved: Write as 0. Ignore on read. 4 XPOL: Polarity state of the 10Base- Normal polarity 1 - Reversed polarity 3:0 Reserved: Read only - Writing to these bits have no effect. SMSC LAN9221/LAN9221i 27 Size: DESCRIPTION 125 DATASHEET 16-bits MODE DEFAULT RW ...
Page 126
... Mask Bits interrupt source is enabled 0 = interrupt source is masked Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 29 Size: DESCRIPTION 30 Size: DESCRIPTION 126 DATASHEET Datasheet 16-bits TYPE DEFAULT RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH See Note 5.5 RO/LH 0 RO/LH 0 RO/LH 0 RO/LH 0 16-bits TYPE DEFAULT SMSC LAN9221/LAN9221i ...
Page 127
... Speed Indication. HCDSPEED value: [001]=10Mbps half-duplex [101]=10Mbps full-duplex [010]=100Base-TX half-duplex [110]=100Base-TX full-duplex 1-0 Reserved. Write as 0; ignore on Read Note 5.6 The default value of this bit is determined by the auto-negotiation process. SMSC LAN9221/LAN9221i 31 Size: DESCRIPTION 127 DATASHEET 16-bits TYPE DEFAULT ...
Page 128
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Test load varies dependent on VDDVARIO: VDDVARIO = 3.3V ± 300mV: 25pF VDDVARIO = 2.5V ± 10%: 10pF VDDVARIO=1.8V ± 10%: 10pF Figure 6.1 Equivalent Test Load for commercial version, - +85 128 DATASHEET Datasheet Figure 6.1 below. Note 6 for industrial version. SMSC LAN9221/LAN9221i ...
Page 129
... TX_FIFO_INF PMT_CTRL GPIO_CFG GPT_CFG GPT_CNT WORD_SWAP FREE_RUN SMSC LAN9221/LAN9221i Table 6.1, "Read After Write Timing Table 6.1 also shows the number of dummy reads that Table 6.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) ...
Page 130
... Table 6.2 Read After Read Timing Rules OR PERFORM THIS MANY READS OF BYTE_TEST… (ASSUMING Tcycle OF 45NS) 135 3 135 3 135 3 180 4 130 DATASHEET Datasheet NUMBER OF BYTE_TEST READS (ASSUMING T OF 45NS) CYCLE Rules". The host BEFORE READING... RX_FIFO_INF RX_FIFO_INF TX_FIFO_INF RX_DROP SMSC LAN9221/LAN9221i ...
Page 131
... Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. SMSC LAN9221/LAN9221i Figure 6.2 PIO Read Cycle Timing Table 6.3 PIO Read Timing time is 9ns ...
Page 132
... High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Figure 6.3 PIO Burst Read Cycle Timing Table 6.4 PIO Burst Read Timing time is 9ns. doff 132 DATASHEET Datasheet MIN TYP MAX UNITS Note 6 time is 7ns. When VDDVARIO is doff SMSC LAN9221/LAN9221i ...
Page 133
... When VDDVARIO is 3.3V or 2.5V, the maximum T 1.8V, the maximum T Note Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de- asserted in any order. SMSC LAN9221/LAN9221i MIN ...
Page 134
... The cycle ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any order. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O MIN time is 7ns. When VDDVARIO is doff time is 9ns. doff 134 DATASHEET Datasheet TYP MAX UNITS Note 6.5 ns SMSC LAN9221/LAN9221i ...
Page 135
... Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. SMSC LAN9221/LAN9221i Figure 6.6 PIO Write Cycle Timing Table 6.7 PIO Write Cycle Timing ...
Page 136
... Note Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order. Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O MIN 136 DATASHEET Datasheet TYP MAX UNITS SMSC LAN9221/LAN9221i ...
Page 137
... Note: Power must be applied and removed to all 3.3V power supply pins simultaneously (including the Ethernet magnetics). Note: Power must be applied and removed to all VDDVARIO power supply pins simultaneously. SMSC LAN9221/LAN9221i t pon Figure 6.8 Power Sequence Timing Table 6.9 Power Sequence Timing ...
Page 138
... Output Drive after nRESET rising Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O T6.1 T6.2 T6.3 T6.4 Figure 6.9 Reset Timing Table 6.10 Reset Timing MIN TYP MAX 30 200 10 16 138 DATASHEET Datasheet UNITS NOTES SMSC LAN9221/LAN9221i ...
Page 139
... EECLK low to data disable (OUTPUT) CKLDIS t EEDIO valid after EECS high (VERIFY) CSHDV t EEDIO hold after EECS low (VERIFY) DHCSL t EECS low CSL SMSC LAN9221/LAN9221i Figure 6.10 EEPROM Timing Table 6.11 EEPROM Timing Values MIN 1110 550 550 1070 30 550 550 ...
Page 140
... for commercial version, - +85 Conditions**", Section 7.6, "DC Electrical ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 140 DATASHEET Datasheet 7. +3.6V 7. +6V 7. -0.5V Note 7 +150 o C for industrial version. Specifications", or any other Note 7.4 SMSC LAN9221/LAN9221i o C ...
Page 141
... D2, General Power Down 100BASE-TX Operation D0, 100BASE-TX /w traffic D0, Idle D1, Idle D2, Energy Detect Power Down (Cable disconnected) D2, General Power Down Note 7 Normal Operation WOL (Wake On LAN mode), D2= Low Power Energy Detect. SMSC LAN9221/LAN9221i MODE 141 DATASHEET Total Power - Typical (mW) 249 243 146 64 11 ...
Page 142
... Operation D0, 100BASE-TX /w traffic D0, Idle D1, Idle D2, Energy Detect Power Down D2, General Power Down Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O Total Power - Typical (mW) 142 DATASHEET Datasheet 596 591 492 64 11 522 510 416 64 11 SMSC LAN9221/LAN9221i ...
Page 143
... Variable Voltage Supply Current +3.3V Regulator Supply Current +3.3V Analog Supply Current Note: Above values do not include the supply current for the magnetics. Based on the recommended implementation, the maximum supply current needed for the magnetics is 108mA. SMSC LAN9221/LAN9221i Table 7. for commercial version, -40 ...
Page 144
... VDDVARIO - 0.4 -0.3 1.4 144 DATASHEET Datasheet for more information. UNITS NOTES V 5 Schmitt Trigger V Schmitt Trigger 492 mV +10 uA Note 7.8 120 uA Note 7.8, Note 7.9 2 12mA -12mA OH 0 12mA OL 0 8mA OL 0 8mA -8mA OH 0.5 V 3.6 V SMSC LAN9221/LAN9221i ...
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... V OL VO8 Type Buffer Low Output Level V OL High Output Level V OH ICLK Input Buffer Low Input Level V ILCK High Input Level V IHCK SMSC LAN9221/LAN9221i MIN TYP MAX -0.3 0.78 0.94 1.13 1.32 1.51 304 384 -10 IN VDDVARIO - 0.4 VDDVARIO - 0.4 -0 ...
Page 146
... MAX to calculate per-pin leakage. For example pins IN 146 DATASHEET Datasheet UNITS NOTES Schmitt Trigger V Schmitt Trigger 525 mV +10 uA Note 7.8 120 uA Note 7.8, Note 7.9 2 4mA -4mA OH 0 4mA OL 0 3mA OL 0 3mA -3mA OH 0.5 V 3.6 V Chapter 2, Pin (5.5V or 5.25V, dependant on IN SMSC LAN9221/LAN9221i ...
Page 147
... Note 7.11 Offset from16 nS pulse width at 50% of pulse peak Note 7.12 Measured differentially. Table 7.10 10BASE-T Transceiver Characteristics PARAMETER Transmitter Peak Differential Output Voltage Receiver Differential Squelch Threshold Note 7.13 Min/Max voltages guaranteed as measured with 100Ω resistive load. SMSC LAN9221/LAN9221i SYMBOL MIN TYP MAX V 950 - 1050 ...
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... L P 300 - Note 7. typ - 3 typ o C for industrial version for industrial version. 148 DATASHEET Datasheet Table 7.11, "LAN9221/LAN9221i MAX UNITS NOTES - MHz +/-50 PPM Note 7.14 +/-50 PPM Note 7.14 - PPM Note 7.15 +/-50 PPM Note 7. Ohm o Note 7. Note 7. Note 7.19 SMSC LAN9221/LAN9221i ...
Page 149
... Position tolerance of each terminal and exposed pad is ± 0. maximum material condition. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip. 3. The pin 1 identifier may vary, but is always located within the zone indicated. SMSC LAN9221/LAN9221i MAX REMARKS 1.00 Overall Package Height 0 ...
Page 150
... Figure 8.2 56 Pin QFN Recommended PCB Land Pattern Revision 2.7 (03-15-10) High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O 150 DATASHEET Datasheet SMSC LAN9221/LAN9221i ...
Page 151
... Power Signals,” on page 18 Rev. 2.2 Auto-negotiation Advertisement on page 121 (06-10-08) SMSC LAN9221/LAN9221i Table 9.1 Customer Revision History Added pin 1 designator to pin diagram Added note: “Do not drive input signals without power supplied to the device.” Added power sequence timing section ...
Page 152
... Removed the system memory block and arrow above the microprocessor/ microcontroller Pin assignment information re-organized into separate table. Note added to EECLK pin description to indicate proper usage. 152 DATASHEET Datasheet CORRECTION WUCSR—Wake- Register, a broadcast wake- Register.” SMSC LAN9221/LAN9221i ...