EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 65
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
3.13.2
RX Packet Format
The RX status words can be read from the RX status FIFO port, while the RX data packets can be
read from the RX data FIFO. RX data packets are formatted in a specific manner before the host can
read them as shown in
status word from the RX status FIFO, to ascertain the data size and any error conditions.
Figure 3.21
appended to the data payload is treated just as an additional 4-bytes within the RX Data FIFO. The
RX checksum is enabled by setting the RXCOE_EN bit in the
Control
Checksum Offload Engine
Register. For more information on the RX checksum, refer to
shows the RX packet format when the RX checksum is enabled. The RX checksum data
Host Read
Order
Last
2nd
1st
Figure
(RXCOE)".
Figure 3.20 RX Packet Format
3.20. It is assumed that the host has previously read the associated
31
ofs + First Data DWORD
Optional offset DWORDn
Optional offset DWORD0
DATASHEET
Optional Pad DWORD0
Optional Pad DWORDn
Last Data DWORD
65
.
.
.
.
.
.
.
.
0
COE_CR—Checksum Offload Engine
Section 3.6.1, "Receive
Revision 2.7 (03-15-10)
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