EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 32

• Manufacturer Part Number: EVB9221-MINI
• Description: EVALUATION BOARD LAN9221-ABZJ
• Manufacturer: SMSC

Specifications of EVB9221-MINI

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: LAN9221
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
• Processor To Be Evaluated: LAN9221
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1074

Revision 2.7 (03-15-10)
1DWORD
1DWORD
DST
0
The RXCOE supports a maximum of two VLAN tags. If there are more than two VLAN tags, the VLAN
protocol identifier for the third tag is treated as an Ethernet type field. The checksum calculation will
begin immediately after the type field.
The RXCOE resides in the RX path within the MAC. As the RXCOE receives an Ethernet frame it
calculates the 16-bit checksum. The RXCOE passes the Ethernet frame to the RX Data FIFO with the
checksum appended to the end of the frame. The RXCOE inserts the checksum immediately after the
last byte of the Ethernet frame. The packet length field in the RX status word (refer to
will indicate that the frame size has increased by two bytes to accommodate the checksum.
Setting the RXCOE_EN bit in the
RXCOE, while the RXCOE_MODE bit selects the operating mode. When the RXCOE is disabled, the
the received data is simply passed through the RXCOE unmodified.
Note: Software applications must stop the receiver and flush the RX data path before changing the
Note: When the RXCOE is enabled, automatic pad stripping must be disabled (bit 8 (PADSTR) of
DST
0
1
SRC
Figure 3.9 Ethernet Frame with multiple VLAN Tags and SNAP Header
1
{DSAP, SSAP, CTRL,
state of the RXCOE_EN or RXCOE_MODE bits.
the
simultaneously.
SRC
2
{DSAP, SSAP, CTRL,
2
OUI[23:16]}
Figure 3.8 Ethernet Frame with VLAN Tag and SNAP Header
MAC_CR—MAC Control
8
1
0
0
4
OUI[23:16]}
8
1
0
0
V
I
D
3
V
I
D
8
1
0
0
5
L
e
n
V
I
D
4
L
e
n
S
N
A
P
0
6
S
N
A
P
0
5
S
N
A
P
1
7
S
N
A
P
1
6
8
COE_CR—Checksum Offload Engine Control Register
DATASHEET
{OUI[15:0], PID[15:0]}
Register) and vice versa. These functions cannot be enabled
{OUI[15:0], PID[15:0]}
32
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Calculate Checksum
Calculate Checksum
L3 Packet
L3 Packet
SMSC LAN9221/LAN9221i
C
F
S
Section
F
C
S
enables the
Datasheet
3.13.3)