EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 40
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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Revision 2.7 (03-15-10)
3.9.2.1
If an operation is attempted, and an EEPROM device does not respond within 30mS, the
LAN9221/LAN9221i will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be
set.
Figure 3.4, "EEPROM Access Flow Diagram"
EEPROM Read or Write operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
page 103
Busy Bit = 0
for E2P_CMD field settings for each command.
EEPROM Write
Figure 3.4 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
40
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
illustrates the host accesses required to perform an
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
SMSC LAN9221/LAN9221i
Datasheet
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