EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 14
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
1.11
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as
an interface for the LAN9221/LAN9221i Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface
models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface.
Programmed I/O transactions are supported.
The LAN9221/LAN9221i host bus interface supports 16-bit bus transfers. Internally, all data paths are
32-bits wide. The LAN9221/LAN9221i can be interfaced to either Big-Endian or Little-Endian
processors and includes mixed endian support for FIFO accesses.
14
Revision 2.7 (03-15-10)
SMSC LAN9221/LAN9221i
DATASHEET
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