EVAL-ADUC831QSZ Analog Devices Inc, EVAL-ADUC831QSZ Datasheet - Page 44

• Manufacturer Part Number: EVAL-ADUC831QSZ
• Description: KIT DEV FOR ADUC831 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC831QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC831
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC831
• Lead Free Status / Rohs Status: Compliant
• Other names: EVAL-ADUC831QS; EVAL-ADUC831QS

ADuC831
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device
reset or interrupt within a reasonable amount of time if the
ADuC831 enters an erroneous state, possibly due to a program-
ming error or electrical noise. The watchdog function can be
disabled by clearing the WDE (Watchdog Enable) bit in the
Watchdog Control (WDCON) SFR. When enabled, the watch-
dog circuit will generate a system reset or interrupt (WDS) if
the user program fails to set the watchdog (WDE) bit within a
WDCON
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Name
PRE3
PRE2
PRE1
PRE0
WDIR
WDS
WDE
WDWR
Watchdog Timer Control Register
C0H
10H
Yes
Description
Watchdog Timer Prescale Bits.
The Watchdog timeout period is given by the equation: t
(0 ≤ PRE ≤ 7; f
PRE3 PRE2 PRE1
0
0
0
0
0
0
0
0
1
PRE3–0 > 1000
Watchdog Interrupt Response Enable Bit.
If this bit is set by the user, the watchdog will generate an interrupt response instead of a
system reset when the watchdog timeout period has expired. This interrupt is not disabled by
the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not
being used to monitor the system, it can alternatively be used as a timer. The prescaler is used
to set the timeout period in which an interrupt will be generated.
Watchdog Status Bit.
Set by the Watchdog Controller to indicate that a watchdog timeout has occurred.
Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset.
Watchdog Enable Bit.
Set by the user to enable the watchdog and clear its counters. If this bit is not set by the user
within the watch dog timeout period, the watchdog will generate a reset or interrupt, depending
on WDIR. Cleared under the following conditions, user writes “0,” Watchdog Reset (WDIR = “0”);
Hardware Reset; PSM Interrupt.
Watchdog Write Enable Bit.
To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit
must be set and the very next instruction must be a write instruction to the WDCON SFR.
For example:
0
0
0
0
1
1
1
1
0
CLR
SETB WDWR
MOV
SETB EA
Table XV. WDCON SFR Bit Designations
0
0
1
1
0
0
1
1
0
EA
WDCON, #72H ;enable WDT for 2.0s timeout
R/C OSC
= 32 kHz
PRE0 Timeout Period (ms) Action
0
1
0
1
0
1
0
1
0
–44–
15.6
31.2
62.5
125
250
500
1000
2000
0.0
;disable interrupts while writing
;allow write to WDCON
;enable interrupts again (if rqd)
predetermined amount of time (see PRE3–0 bits in WDCON).
The watchdog timer itself is a 16-bit counter that is clocked at
32 kHz by the internal R/C oscillator. The watchdog time out
interval can be adjusted via the PRE3–0 bits in WDCON. Full
control and status of the watchdog timer function can be con-
trolled via the watchdog timer control SFR (WDCON). The
WDCON SFR can only be written by user software if the
double write sequence described in WDWR below is initiated
on every write access to the WDCON SFR.
10% at 25ºC)
;to WDT
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Reset or Interrupt
Immediate Reset
Reserved
WD
= (2
PRE
(2
9
/f
R/C OSC
))
REV. 0