EVAL-ADUC831QSZ Analog Devices Inc, EVAL-ADUC831QSZ Datasheet - Page 62

• Manufacturer Part Number: EVAL-ADUC831QSZ
• Description: KIT DEV FOR ADUC831 QUICK START
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC831QSZ

• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: 8051
• Silicon Core Number: ADuC831
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC831
• Lead Free Status / Rohs Status: Compliant
• Other names: EVAL-ADUC831QS; EVAL-ADUC831QS

ADuC831
As an alternative to providing two separate power supplies, the
user can help keep AV
and/or ferrite bead between it and DV
AV
shown in Figure 61. With this configuration other analog circuitry
(such as op amps, voltage reference, and so on) can be powered
from the AV
include back-to-back Schottky diodes between AV
in order to protect from power-up and power-down transient con-
ditions that could separate the two supply voltages momentarily.
Notice that in both Figure 60 and Figure 61, a large value (10 µF)
reservoir capacitor sits on DV
sits on AV
each V
to include all of these capacitors, and ensure the smaller capacitors
are close to each AV
Connect the ground terminal of each of these capacitors directly to
the underlying ground plane. Finally, it should also be noted that,
at all times, the analog and digital ground pins on the ADuC831
must be referenced to the same system ground reference point.
Power Consumption
The currents consumed by the various sections of the ADuC831
are shown in Table XXXIII. The CORE values given represent
the current drawn by DV
ref) are pulled by the AV
when not in use. The other on-chip peripherals (watchdog timer,
power supply monitor, and so on) consume negligible current
and are therefore lumped in with the Core operating current here.
Of course, the user must add any currents sourced by the parallel
and serial I/O pins, and that sourced by the DAC, in order to
determine the total current needed at the ADuC831’s supply pins.
Also, current drawn from the DV
approximately 10 mA during Flash/EE erase and program cycles.
Core:
Core:
ADC:
DAC (Each):
Voltage Ref:
(Normal Mode) (1.6 nAs
(Idle Mode)
DD
Figure 61. External Single-Supply Connections
separately to ground. An example of this configuration is
DD
Table XXXIII. Typical I
DD
pin of the chip. As per standard design practice, be sure
DIGITAL SUPPLY
0.1 F
. Also, local small-value (0.1 µF) capacitors are located at
+
–
DD
supply line as well. The user will still want to
10 F
DD
V
6 mA
(0.75 nAs
5 mA
1.3 mA
250 µA
200 µA
DD
DD
pin with trace lengths as short as possible.
DD
quiet by placing a small series resistor
= 5 V
DD
, while the rest (ADC, DAC, voltage
pin and can be disabled in software
DD
DV
DGND
BEAD
DD
DD
M
ADuC831
M
and a separate 10 µF capacitor
DD
of Core and Peripherals
CLK
CLK
supply will increase by
1.6V
DD
) +
) +
AGND
AV
, and then decoupling
DD
V
(0.8 nAs
3 mA
(0.25 nAs
3 mA
1.0 mA
200 µA
150 µA
DD
10 F
= 3 V
0.1 F
DD
and DV
M
M
CLK
CLK
) +
)+
DD
–62–
Since operating DV
speed, the expressions for CORE supply current in Table XXXIII
are given as functions of M
a value for M
the core at that oscillator frequency. Since the ADC and DACs
can be enabled or disabled in software, add only the currents
from the peripherals you expect to use. And again, do not forget
to include current sourced by I/O pins, serial port pins, DAC
outputs, and so forth, plus the additional current drawn during
Flash/EE erase and program cycles.
A software switch allows the chip to be switched from normal
mode into idle mode, and also into full power-down mode.
Below are brief descriptions of power-down and idle modes.
Power Saving Modes
In idle mode, the oscillator continues to run but is gated off to the
core only. The on-chip peripherals continue to receive the clock,
and remain functional. Port pins and DAC output pins retain their
states in this mode. The chip will recover from idle mode upon
receiving any enabled interrupt, or on receiving a hardware reset.
In full power-down mode, the on-chip oscillator stops and all
on-chip peripherals are shut down. Port pins retain their logic
levels in this mode, but the DAC output goes to a high-impedance
state (three-state). During full power-down mode, the ADuC831
consumes a total of approximately 15 µA. There are five ways of
terminating power-down mode:
Asserting the RESET Pin (Pin 15)
Returns to normal mode. All registers are set to their default
state and program execution starts at the reset vector once the
Reset pin is de-asserted.
Cycling Power
All registers are set to their default state and program execution
starts at the reset vector approximately 128 ms later.
Time Interval Counter (TIC) Interrupt
Power-down mode is terminated and the CPU services the TIC
interrupt. The RETI at the end of the TIC ISR will return the
core to the instruction after that which enabled power-down.
I
Power-down mode is terminated and the CPU services the I
interrupt. The RETI at the end of the ISR will return the core to
the instruction after that which enabled power-down. It should be
noted that the I
in the PCON SFR must first be set to allow this mode of operation.
INT0 Interrupt
Power-down mode is terminated and the CPU services the INT0
interrupt. The RETI at the end of the ISR will return the core
to the instruction after that which enabled power-down. It should
be noted that the INT0 power-down interrupt enable bit (INT0PD)
in the PCON SFR must first be set to allow this mode of operation.
Power-On Reset
An internal POR (Power-On Reset) is implemented on the
ADuC831. For DV
the ADuC831 in reset. As DV
timer will timeout for approximately 128 ms before the part is
released from reset with a 16 MHz crystal. With other crystal
values the timeout will increase. The user must ensure that the
power supply has reached a stable 2.7 V minimum level by this
time. Likewise on power-down, the internal POR will hold the
ADuC831 in reset until the power supply has dropped below 1 V.
Figure 62 illustrates the operation of the internal POR in detail.
2
C or SPI Interrupt
CLK
2
C/SPI power down interrupt enable bit (SERIPD)
in hertz to determine the current consumed by
DD
DD
below 2.45 V, the internal POR will hold
current is primarily a function of clock
CLK
DD
, the oscillator frequency. Plug in
rises above 2.45 V an internal
REV. 0
2
C/SPI