DEMO9S08LC60 Freescale Semiconductor, DEMO9S08LC60 Datasheet - Page 86

• Manufacturer Part Number: DEMO9S08LC60
• Description: BOARD DEMO FOR 9S08LC60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S08LC60

• Contents: Evaluation Board
• Processor To Be Evaluated: MC9S08LC60
• Interface Type: RS-232, USB
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08LC
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08LC60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 6 Parallel Input/Output
6.2.2.2
Slew rate control can be enabled for each port pin by setting the corresponding bit in the slew rate control
register (PTASEn). When enabled, slew control limits the rate at which an output can transition in order to
reduce EMC emissions. Slew rate control has no effect on pins which are configured as inputs.
6.2.2.3
An output pin can be selected to have high output drive strength by setting the corresponding bit in the
drive strength select register (PTADSn). When high drive is selected a pin is capable of sourcing and
sinking greater current. Even though every I/O pin can be selected as high drive, the user must ensure that
the total current source and sink limits for the chip are not exceeded. Drive strength selection is intended
to affect the DC behavior of I/O pins. However, the AC behavior is also affected. High drive allows a pin
to drive a greater load with the same switching speed as a low drive enabled pin into a smaller load.
Because of this the EMC emissions may be affected by enabling pins as high drive.
86
PTASE[7:0]
PTADS[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PTASE7
PTADS7
Output Slew Rate Control Enable (
Output Drive Strength Select (
Slew Rate Control Enable for Port A Bits — For port A pins that are outputs, these read/write control bits
determine whether the slew rate controlled outputs are enabled. For port A pins that are configured as inputs,
these bits are ignored.
0 Slew rate control disabled.
1 Slew rate control enabled.
Output Drive Strength Selection for Port A Bits—Each of these control bits selects between low and high output
drive for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Low output drive strength selected for port A bit n.
1 High output drive strength selected for port A bit n.
1
0
7
7
PTASE6
PTADS6
Figure 6-8. Slew Rate Control Enable for Port A (PTASE)
Figure 6-9. Drive Strength Selection for Port A (PTADS)
1
0
6
6
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table 6-4. PTASE Field Descriptions
Table 6-5. PTADS Field Descriptions
PTASE5
PTADS5
1
0
5
5
PTADS4
PTASE4
1
0
4
4
PTADS)
Description
Description
PTASE)
PTADS3
PTASE3
3
1
3
0
PTASE2
PTADS2
1
0
2
2
PTASE1
PTADS1
Freescale Semiconductor
1
0
1
1
PTASE0
PTADS0
1
0
0
0