M68EVB908GB60E Freescale Semiconductor, M68EVB908GB60E Datasheet - Page 58

• Manufacturer Part Number: M68EVB908GB60E
• Description: BOARD EVAL FOR MC9S08GB60
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of M68EVB908GB60E

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC9S08GB
• Data Bus Width: 8 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08
• Core Sub-architecture: HCS08
• Silicon Core Number: MC9S08
• Silicon Family Name: S08GB
• Kit Contents: GB60 Evaluation Kit
• Rohs Compliant: Yes
• For Use With/related Products: MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 4 Memory
4.6.5
Bits 3, 1, and 0 always read 0 and writes have no meaning or effect. The remaining five bits are status bits
that can be read at any time. Writes to these bits have special meanings that are discussed in the bit
descriptions.
FCBEF — FLASH Command Buffer Empty Flag
FCCF — FLASH Command Complete Flag
FPVIOL — Protection Violation Flag
FACCERR — Access Error Flag
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The FCBEF bit is used to launch commands. It also indicates that the command buffer is empty so that
a new command sequence can be executed when performing burst programming. The FCBEF bit is
cleared by writing a 1 to it or when a burst program command is transferred to the array for
programming. Only burst program commands can be buffered.
FCCF is set automatically when the command buffer is empty and no command is being processed.
FCCF is cleared automatically when a new command is started (by writing 1 to FCBEF to register a
command). Writing to FCCF has no meaning or effect.
FPVIOL is set automatically when FCBEF is cleared to register a command that attempts to erase or
program a location in a protected block (the erroneous command is ignored). FPVIOL is cleared by
writing a 1 to FPVIOL.
FACCERR is set automatically when the proper command sequence is not followed exactly (the
erroneous command is ignored), if a program or erase operation is attempted before the FCDIV register
has been initialized, or if the MCU enters stop while a command was in progress. For a more detailed
discussion of the exact actions that are considered access errors, see
FACCERR is cleared by writing a 1 to FACCERR. Writing a 0 to FACCERR has no meaning or effect.
1 = A new burst program command may be written to the command buffer.
0 = Command buffer is full (not ready for additional commands).
1 = All commands complete
0 = Command in progress
1 = An attempt was made to erase or program a protected location.
0 = No protection violation.
1 = An access error has occurred.
0 = No access error has occurred.
FLASH Status Register (FSTAT)
Reset:
Read:
Write:
FCBEF
Bit 7
1
Figure 4-8. FLASH Status Register (FSTAT)
= Unimplemented or Reserved
MC9S08GB/GT Data Sheet, Rev. 2.3
FCCF
6
1
FPVIOL FACCERR
5
0
4
0
3
0
0
Section 4.4.5, “Access
FBLANK
2
0
Freescale Semiconductor
1
0
0
Bit 0
0
0
Errors.”