Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 143

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

Table 89. Read Status Byte
BITS
FIELD
DEFAULT
VALUE
PS026308-1207
Power Failure Protection
Because of the Flash memory architecture, NVDS reads exhibit a non-uniform execution
time. A read operation takes between 71 μs and 258 μs (assuming a 20 MHz system
clock). Slower system clock speeds result in proportionally higher execution times.
NVDS byte reads from invalid addresses (those exceeding the NVDS array size) return
0xff
The status byte returned by the NVDS read routine is zero for successful read. If the status
byte is non-zero, there is a corrupted value in the NVDS array at the location being read.
In this case, the value returned in R0 is the byte most recently written to the array that does
not have an error.
The NVDS routines employ error checking mechanisms to ensure a power failure
endangers only for the most recently written byte. Bytes previously written to the array are
not perturbed. For this protection to function, the VBO must be enabled (See
Modes
Bit Address Space
A system reset (such as a pin reset or Watchdog Timer reset) that occurs during a Write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
7
0
Reserved—Must be 0.
DE—Data Error
When reading a NVDS address, if an error is found in the latest data corresponding to
this NVDS address, this bit is set to 1. NVDS source code steps forward until finding
a valid data at this address.
FE—Flash Error
If Flash error is detected, this bit is set to 1.
IGADDR—Illegal address
When NVDS byte reads from invalid addresses (those exceeding the NVDS array
size) occur, this bit is set to 1.
. Illegal read operations have a 6 μs execution time.
on page 33) and configured for a threshold voltage of 2.4 V or greater (See
Reserved
6
0
on page 124).
5
0
DE
4
0
Reserved
3
0
Z8 Encore!
FE
2
0
Product Specification
Non Volatile Data Storage
IGADDR Reserved
®
1
0
F083A Series
Low-Power
Trim
0
0
131