Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 95

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PS026308-1207
TEN—Timer enable
0 = Timer is disabled.
1 = Timer enabled to count.
TPOL—Timer input/output polarity
Operation of this bit is a function of the current operating mode of the timer.
ONE-SHOT Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled, the timer output signal is complemented on timer reload.
CONTINUOUS Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled and reloaded, the timer output signal is complemented.
COUNTER Mode
If the timer is disabled, the timer output signal is set to the value of this bit.
If the timer is enabled the timer output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the timer input signal.
1 = Count occurs on the falling edge of the timer input signal.
PWM SINGLE OUTPUT Mode
0 = Timer output is forced low (0), when the timer is disabled. The timer output is
forced high (1), when the timer is enabled and the PWM count matches and the timer
output is forced low (0), when the timer is enabled and reloaded.
1 = Timer output is forced high (1), when the timer is disabled. The timer output is
forced low(0), when the timer is enabled and the PWM count matches and forced high
(1) when the timer is enabled and reloaded.
CAPTURE Mode
0 = Count is captured on the rising edge of the timer input signal.
1 = Count is captured on the falling edge of the timer input signal.
COMPARE Mode
When the timer is disabled, the timer output signal is set to the value of this bit. When
the timer is enabled and reloaded, the timer output signal is complemented.
GATED Mode
0 = Timer counts when the timer input signal is high (1) and interrupts are generated
on the falling edge of the timer input.
1 = Timer counts when the timer input signal is low (0) and interrupts are generated on
the rising edge of the timer input.
CAPTURE/COMPARE Mode
0 = Counting is started on the first rising edge of the timer input signal. The current
count is captured on subsequent rising edges of the timer input signal.
1 = Counting is started on the first falling edge of the timer input signal. The current
count is captured on subsequent falling edges of the timer input signal.
Z8 Encore!
Product Specification
®
F083A Series
Timers
83