Z8F083A0128ZCOG Zilog, Z8F083A0128ZCOG Datasheet - Page 68

• Manufacturer Part Number: Z8F083A0128ZCOG
• Description: KIT DEVELOPMENT F083A
• Manufacturer: Zilog
• Series: Z8 Encore! XP®r
• Type: MCUr

Specifications of Z8F083A0128ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F083A
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4672

PS026308-1207
Caution:
Interrupt Vectors and Priority
Interrupt Assertion
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Interrupts are globally disabled by any of the following actions:
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The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, level 2 is the second highest priority, and level 1 is the lowest priority. If all the
interrupts are enabled with identical interrupt priority (all as level 2 interrupts, for
example), the interrupt priority is assigned from highest to lowest as specified in
on page 54. Level 3 interrupts are always assigned higher priority than level 2 interrupts
and level 2 interrupts are assigned higher priority than level 1 interrupts. Within each
interrupt priority level (level 1, level 2, or level 3), priority is assigned as specified in
Table 31
oscillator fail trap, Watchdog oscillator fail trap, and illegal instruction trap always have
highest (level 3) priority.
Interrupt sources assert their interrupt requests for only a single system clock period
(single pulse). When the interrupt request is acknowledged by the eZ8 CPU, the
corresponding bit in the interrupt request register is cleared. Writing 0 to the
corresponding bit in the interrupt request register clears the interrupt request.
The coding style listed below that clears the bits in the interrupt request registers is Not
recommended. All incoming interrupts received between execution of the first
command and the final
Execution of an IRET (return from interrupt) instruction
Writing 1 to the IRQE bit in the interrupt control register
Execution of a DI (disable interrupt) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the interrupt control register
Reset
Execution of a trap instruction
Illegal instruction Trap
Primary oscillator fail trap
Watchdog oscillator fail trap
on page 54, above. Reset, Watchdog Timer interrupt (if enabled), primary
Poor coding style that results in lost interrupt requests:
LDX r0, IRQ0
LDX
command are lost.
Z8 Encore!
Product Specification
®
Interrupt Controller
F083A Series
Table 31
LDX
56