MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 143
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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C
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1
W ATA_
V
Y
_DAT
See
GND
ATA3
NFC
NFR
SRX
I2C2
FEC
_RD
E_B
RTS
FST
STX
D14
TX1
D5
D8
LE
D5
D4
DATA
1
2
ATA_
DA1
VSS
14
1
Table 92
NFAL
TX3_
NFW
ATA1
TXD
HCK
FEC
_RD
D10
D15
E_B
RX2
STX
FS4
STX
D0
D2
D7
D4
DATA
DATA
E
R
ATA_
INTR
ATA_
ATA_
2
2
13
11
Q
2
_CLK
_RX_
TX5_
RXD
I2C2
ATA2
ERR
NFR
SCK
FEC
_RD
FEC
A13
D12
NF_
CE0
RX0
D4
D6
A9
DATA
ATA_
DATA
DATA
ATA_
ATA_
B
R
3
2
Table 93. Silicon Revision 2.0 Ball Map—17 x 17, 0.8 mm Pitch
for pins unavailable in the MCIMX351 SoC.
10
3
9
7
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
_TDA
NFW
TX4_
_TX_
SCK
MA1
RX1
SRX
SCK
FEC
FEC
ERR
P_B
TX0
TA1
D1
D9
D5
A7
A8
ATA_
DATA
ATA_
DATA
ATA_
DATA
4
0
T
4
4
6
5
4
Table 94. Silicon Revision 2.1 Ball Map—17 x 17, 0.8 mm Pitch
_TDA
TX2_
HCK
CTS
RX3
FSR
SCK
FEC
FEC
_CR
A11
D13
TA2
DATA
DATA
DATA
A0
A5
A6
D3
ATA_
ATA_
ATA_
5
T
S
2
5
5
2
1
0
C_MI
_TDA
C_AT
SDB
SDB
NVC
NVC
NVC
VDD
NVC
C_N
C_N
STX
FS5
FEC
D11
A12
TA3
SC
ATA_
DMA
ATA_
ATA_
A0
A1
A3
A4
FC
FC
DIO
DIO
A
6
2
CK
W
6
R
SD30 SD27 SD24 SD23 SD21 SD18 SD15 SD14 SD10
SD31 SD28 SD26 SD22 SD20 SD19 SD12 SD13 SD11
C_MI
GND
VDD
NVC
NVC
C_N
VDD
NVC
VDD
VDD
C_E
A23
MI1
ATA_
USB
OTG
_PW
ODE
FC
SC
CS0
TES
T_M
A1
A2
7
7
1
2
3
R
7
SD29 SD25
C_MI
GND
GND
GND
GND
GND
VDD
NVC
NVC
CSPI
CSPI
C_E
A24
A25
MCL
MI1
EXT
_AR
1_S
CLK
1_S
SC
S0
8
7
K
8
SDQ
GND
GND
GND
GND
GND
CSPI
CSPI
POW
VDD
NVC
NVC
1_MI
A22
C_E
C_E
1_M
ER_
FAIL
MI1
MI1
OSI
SO
S3
9
7
9
BOO
SDQ
GND
NVC
NVC
GND
GND
GND
GND
GND
ODE
_MO
C_E
C_E
CLK
T_M
CLK
DE0
A20
A21
MI1
MI1
10
S2
10
O
0
SD17 SD16
POR
MGN
SDQ
NVC
NVC
GND
GND
GND
GND
O3_
O1_
C_E
C_E
FUS
GPI
GPI
A19
E_V
MI1
MI1
_B
S1
SS
11
11
0
1
D
_SIG
OG_
CAP
TUR
MLB
RST
GND
GND
GND
GND
GND
SDC
VDD
NVC
PGN
WD
C_E
A18
MI2
12
LK
12
E
D
7
_DAT
_DAT
MLB
MLB
SD2
LK_B
_CL
GND
GND
GND
GND
SDC
NVC
VDD
NVC
PVD
C_E
C_E
A0
A17
A16
13
MI2
MI2
K
13
D
6
_DAT
CSI_
HSY
SD2
_CL
SD2
LD16 LD22 LD20 LD21 LD18 LD17 LD19
1_UP
GND
NC
SDQ
NVC
NVC
CDC
NVC
CDC
NVC
CDC
NVC
CDC
USB
PHY
A2
SD8
C_E
LLG
14
A14
MI3
C_L
C_L
C_L
C_L
K
ND
S0
14
PIXC
CSI_
CSI_
MCL
CSI_
D13
1_VD
1_UP
SDW
D3_F
PSHI
LLVD
15
LK
SD5
BCL
VDD
VDD
PHY
USB
PHY
A15
A10
K
DA
FT
15
K
E
D
5
5
1
CSI_
CSI_
CSI_
D10
D12
D15
_PAD
DQM
LD12 LD14 LD11 LD13 LD15
1_VS
16
CON
(continued)
SD9
SD7
RAS
TRA
TTM
PHY
SD3
EB1
LD3
LD5
SA
16
ST
2
_DAT
CSI_
USB
PHY
SD1
2_D
17
A3
D9
DQM
_DAT
M
SDC
I2C1
SD6
SD0
CAS
CS0
CLS
REV
KE1
LD2
LD8
D3_
D3_
17
1
_DAT
SD1
SD1
USB
PHY
_CL
2_D
A2
18
D3_S
DQM
K
P
SDC
1_UI
SD4
SD2
KE0
CS4
EB0
HSY
USB
PHY
LD1
LD6
D3_
NC
PL
18
D
3
XTAL
_CM
_AU
DE_
SD1
DIO
19
D
DQM
D3_V
B
LD23
ECB
SYN
USB
PHY
SD1
CS3
CS1
CS5
LD4
LD9
1_D
19
C
M
0
DIO_
AUDI
OSC
VDD
VSS
_AU
EXT
AL_
20
O
_CLK
1_VD
LD10
GND
DRD
I2C1
PHY
CS2
LBA
LD0
LD7
D3_
RW
OE
DA
20
Y
W
V
Y
143
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