MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 37

• Manufacturer Part Number: MCIMX35WPDKJ
• Description: BOARD DEV FOR I.MX35
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r
• Type: MPUr

Specifications of MCIMX35WPDKJ

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: i.MX35
• Processor Series: i.MX35
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, JTAG
• Core: ARM11
• For Use With/related Products: i.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Freescale Semiconductor
“High” is defined as 80% of signal value, and “low” is defined as 20% of signal value.
BCLK parameters are measured from the 50% point. For example, “high” is defined as 50% of signal value and “low” is defined
as 50% of signal value.
Parameters W18, W20, W22, and W24 are tested when FCE=1. i.MX35 does not support FCE=0.
WE10
WE11
WE12
WE13
WE14
WE15
WE16
WE17
WE18
WE19
WE19
WE20
WE22
WE24
WE26
WE27
WE1
WE2
WE3
WE4
WE5
WE6
WE7
WE8
WE9
ID
BCLK cycle time
BCLK low-level width
BCLK high-level width
Clock fall to address valid
Clock rise/fall to address invalid
Clock rise/fall to CSx_B valid
Clock rise/fall to CSx_B invalid
Clock rise/fall to RW_B valid
Clock rise/fall to RW_B invalid
Clock rise/fall to OE_B valid
Clock rise/fall to OE_B invalid
Clock rise/fall to EBy_B valid
Clock rise/fall to EBy_B invalid
Clock rise/fall to LBA_B valid
Clock rise/fall to LBA_B invalid
Clock rise/fall to Output Data valid
Clock rise to Output Data invalid
Input Data Valid to Clock rise
Input Data Valid to Clock rise, FCE=0 (in the case there is ECB_B asserted
during access)
Input Data Valid to Clock rise, FCE=0 (in the case there is NO ECB_B
asserted during access)
Clock rise to Input Data invalid
ECB_B setup time
ECB_B hold time
DTACK_B setup time
DTACK_B hold time
Test conditions: load capacitance, 25 pF. Recommended drive strength for
all controls, address, and BCLK is set to maximum drive.
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
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Table 31. WEIM Bus Timing Parameters
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3
Parameter
NOTE
1
(BCLK/2)
+ 3.01
Min.
14.5
17.5
–3.2
3.6
3.8
6.9
5.4
15
22
15
7
7
8
3
7
6
6
0
5
0
1
1
5
0
Max.
11.5
5.5
2.5
20
10
—
—
—
21
25
19
12
12
10
—
—
—
—
—
—
—
—
5
8
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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