MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 71

• Manufacturer Part Number: MCIMX35WPDKJ
• Description: BOARD DEV FOR I.MX35
• Manufacturer: Freescale Semiconductor
• Series: i.MX35r
• Type: MPUr

Specifications of MCIMX35WPDKJ

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: i.MX35
• Processor Series: i.MX35
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet, USB, CAN, JTAG
• Core: ARM11
• For Use With/related Products: i.MX35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1
Display interface clock period average value.
Figure 51
parameters. The DISP3_IF_CLK_DOWN_WR and DISP3_IF_CLK_UP_WR parameters are set via the
DI_DISP3_TIME_CONF Register.
Freescale Semiconductor
Display interface clock period immediate value
IP10
IP11
IP12
IP13
IP14
IP15
IP9
DISPB_D3_VSYNC
DISPB_D3_HSYNC
DISPB_D3_DRDY
ID
DISPB_D3_CLK
depicts the synchronous display interface timing for access level, and
other controls
Table 52. Synchronous Display Interface Timing Parameters—Pixel Level (continued)
DISPB_DATA
Horizontal blank interval 1
Horizontal blank interval 2
HSYNC delay
Screen height
VSYNC width
Vertical blank interval 1
Vertical blank interval 2
Figure 51. Synchronous Display Interface Timing Diagram—Access Level
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Parameter
IP16
Tdicp
IP17
=
T HSP_CLK
Symbol
IP19
Thbi1
Thbi2
Tvbi1
Tvbi2
Thsd
Tvsw
⋅
Tsh
DISP3_IF_CLK_PER_WR
----------------------------------------------------------------- -
HSP_CLK_PERIOD
IP18
IP20
BGXP × Tdpcp
(SCREEN_WIDTH – BGXP – FW) × Tdpcp
H_SYNC_DELAY × Tdpcp
(SCREEN_HEIGHT + 1) × Tsw
if V_SYNC_WIDTH_L = 0 than
(V_SYNC_WIDTH + 1) × Tdpcp
else
(V_SYNC_WIDTH + 1) × Tsw
BGYP × Tsw
(SCREEN_HEIGHT – BGYP – FH) × Tsw
Value
Table 53
lists the timing
Units
ns
ns
ns
ns
ns
ns
ns
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