MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 92
![BOARD DEV FOR I.MX35](/photos/37/58/375859/imx35_bd_sml.jpg)
MCIMX35WPDKJ
Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets
1.MCIMX35WPDKJ.pdf
(148 pages)
2.MCIMX35WPDKJ.pdf
(2 pages)
3.MCIMX35WPDKJ.pdf
(10 pages)
Specifications of MCIMX35WPDKJ
Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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1
2
3
4
5
6
7
8
92
IP55 Controls hold time for read
IP56 Controls setup time for write
IP57 Controls hold time for write
IP58 Slave device data delay
IP59 Slave device data hold time
IP60 Write data setup time
IP61 Write data hold time
IP62 Read period
IP63 Write period
IP64 Read down time
IP65 Read up time
IP66 Write down time
IP67 Write up time
IP68 Read time point
Tdi cuw
Tdi cdw
Tdi cpw
Tdicdr
Tdi cur
ID
Tdicpr
The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display.
These conditions may be device specific.
Display interface clock period value for read:
Display interface clock period value for write:
Display interface clock down time for read:
Display interface clock up time for read:
Display interface clock down time for write:
Display interface clock up time for write:
This parameter is a requirement to the display connected to the IPU.
=
=
=
=
=
=
1
-- - T HSP_CLK cei l
2
1
-- - T HSP_CLK cei l
2
1
-- - T
2
1
-- - T HSP_CLK cei l
2
T
T
Table 56. Asynchronous Serial Interface Timing Parameters—Access Level (continued)
HSP_CLK
HSP_CLK
HSP_CLK
Parameter
3
2
⋅
⋅
⋅
⋅
⋅
7
c eil
ce il
⋅
5
ce il
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
9
4
6
DISP#_IF_CLK_PER_RD
--------------------------------------------------------------- -
DISP#_IF_CLK_PER_WR
----------------------------------------------------------------- -
2 DISP#_IF_CLK_DOWN_RD
-------------------------------------------------------------------------------
2 DISP#_IF_CLK_UP_WR
--------------------------------------------------------------------- -
2 DISP#_IF_CLK_UP_RD
--------------------------------------------------------------------
2 DISP#_IF_CLK_DOWN_WR
-------------------------------------------------------------------------------- -
⋅
⋅
HSP_CLK_PERIOD
⋅
⋅
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
HSP_CLK_PERIOD
8
8
Symbol
Tdicpw Tdicpw – 1.5
Tdicdw Tdicdw – 1.5
Tdicuw Tdicuw – 1.5
Tdcsw
Tdchw Tdicpw – Tdicdw – 1.5
Tdicpr
Tdicdr
Tdicur
Tdchr
Tracc
Tdrp
Troh
Tds
Tdh
Tdicpr – Tdicdr – 1.5
Tdicuw – 1.5
0
Tdrp – Tlbd – Tdicdr
Tdicdw – 1.5
Tdicpw – Tdicdw – 1.5
Tdicpr – 1.5
Tdicdr – 1.5
Tdicur – 1.5
Tdrp – 1.5
+ 1.5
Min.
Tdicpr – Tdicdr
Tdicuw
Tdicpw – Tdicdw
Tdicdw
Tdicpw – Tdicdw
Tdicpr
Tdicpw
Tdicdr
Tdicur
Tdicdw
Tdicuw
Tdrp
Typ.
—
—
1
Tdrp
Tdicpr – Tdicdr – 1.5
Tdicpr + 1.5
Tdicpw + 1.5
Tdicdr + 1.5
Tdicur + 1.5
Tdicdw + 1.5
Tdicuw + 1.5
Tdrp + 1.5
– 1.5
9
– Tlbd
Freescale Semiconductor
Max.
—
—
—
—
—
10
– Tdicur
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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