MCIMX35WPDKJ Freescale Semiconductor, MCIMX35WPDKJ Datasheet - Page 80

BOARD DEV FOR I.MX35

MCIMX35WPDKJ

Manufacturer Part Number
MCIMX35WPDKJ
Description
BOARD DEV FOR I.MX35
Manufacturer
Freescale Semiconductor
Series
i.MX35r
Type
MPUr
Datasheets

Specifications of MCIMX35WPDKJ

Contents
Module and Misc Hardware
Processor To Be Evaluated
i.MX35
Processor Series
i.MX35
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet, USB, CAN, JTAG
Core
ARM11
For Use With/related Products
i.MX35
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Display read operation can be performed with wait states when each read access takes up to 4 display
interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the
80
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_PAR_RS
DISPB_D#_CS
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_WR
(READ/WRITE)
DISPB_D#_CS
DISPB_WR
(READ/WRITE)
DISPB_BCLK
DISPB_DATA
DISPB_DATA
DISPB_DATA
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
DISPB_RD
(ENABLE)
Figure 57. Asynchronous Parallel System 68k Interface (Type 2) Burst Mode TIming Diagram
Single access mode (all control signals are not active for one display interface clock after each display access)
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 9
Burst access mode with sampling by separate burst clock (BCLK)
Burst access mode with sampling by ENABLE signal
Freescale Semiconductor

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