AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 24

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9549
The resulting loop filter coefficients for the lower loop
bandwidth, along with the necessary programming values,
are shown as follows:
The AD9549 evaluation software generates these coefficients
automatically based on the user’s desired loop characteristics.
CLOSED-LOOP PHASE OFFSET
The AD9549 provides for limited control over the phase offset
between the reference input signal and the output signal by adding
a constant phase offset value to the output of the phase detector.
An adder is included at the output of the phase detector to support
this, as shown in Figure 28. The value of the constant (PLL
is set via the DPLL phase offset bits.
PLL
desired amount of timing offset (Δt
FPFD_Gain is described in the Fine Phase Detector section.
For example, suppose that FPFD_Gain = 200, f
1° of phase offset is desired. First, the value of Δt
determined, as follows:
Having determined Δt
The result has been rounded because PLL
integer values.
Note that the PLL
complement number. However, the user must ensure that the
magnitude is constrained to 12 bits, such that:
The preceding constraint yields a timing adjustment range of
±1 ns. This ensures that the phase offset remains within the
bounds of the fine phase detector.
FEEDBACK
OFFSET
α = 0.005883404361345
α
α
α
β = −0.000003820176667
β
β
γ = −0.00000461136116
γ
γ
PLL
−2
∆
PLL
0
1
2
0
1
0
1
t
= 1542 (0x606)
= 0 (0x00)
= 7 (0x07)
= 16 (0x10)
= 7 (0x07)
= 19 (0x13)
= 7 (0x07)
11
OFFSET
CLK
OFFSET
OFFSET
≤ PLL
is a function of the phase detector gain and the
= Δt
=
OFFSET
=
deg
360
Figure 28. Input Phase Offset Adder
OFFSET
DETECTOR
925
OFFSET
PHASE
< +2
t
9 .
CLK
OFFSET
value is programmed as a 14-bit, twos
(2
ps(
11
10
=
,
2
× 10
10
360
1
OFFSET
PHASE
VALUE
×
7
10



× FPFD_Gain
3
7
OFFSET
MHz
×
1
200
). It is given by
FILTER
LOOP
OFFSET



)
=
=
925
1896
CLK
is restricted to
OFFSET
9 .
= 3 MHz, and
ps
TO CCI
FILTER
must be
OFFSET
Rev. D | Page 24 of 76
)
LOCK DETECTION
Phase Lock Detection
During the phase locking process, the output of the phase
detector tends toward a value of 0, which indicates perfect
alignment of the phase detector input signals. As the control
loop works to maintain the alignment of the phase detector
input signals, the output of the phase detector wanders around 0.
The phase lock detector tracks the absolute value of the digital
samples generated by the phase detector. These samples are
compared to the phase lock detect threshold value (PLDT)
programmed in the I/O register map. A false state at the output
of the comparator indicates that the absolute value of a sample
exceeds the value in the threshold bits. A true state at the output
of the comparator indicates alignment of the phase detector
input signals to the degree specified by the lock detection
threshold.
DETECTOR
The phase lock detect threshold value is a 32-bit number stored
in the I/O register map.
where Δt is the maximum allowable timing error between the
signals at the input to the phase detector and the value of
FPFD_Gain is as described in the Fine Phase Detector section.
For example, suppose that f
the maximum timing deviation is given as 1°. This yields a Δt
value of
The resulting phase lock detect threshold is
Hence, 1896 (0x00000768) is the value that must be stored in
the phase lock detect threshold bits.
REGISTERS
P-DIVIDER
SAMPLES
CLOCK
PHASE
PLDT
∆
PLDT
t
I/O
=
PHASE LOCK DETECT
360
1
=
=
ABSOLUTE
Figure 29. Phase Lock Detector Block Diagram
°
THRESHOLD
VALUE
round
°
round
(
R
×
COMPARATOR
(
T




∆
2
R
DIGITAL
t
10
)
360
×
=
R
×
2
/R = 3 MHz, FPFD_Gain = 200, and
3 (
10
360
10
×
×
R
7
f
10
10
×
R
UNLOCK
TIMER
200
6
7
Y
=
)
CONTROL LOGIC
3
×
360
FPFD




RESET
=
3 (
1896
TIMER
LOCK
1
×
_
10
X
5
Gain
6
CLOSE
LOOP
)
)
PHASE
LOCK
DETECT