AD9549/PCBZ Analog Devices Inc, AD9549/PCBZ Datasheet - Page 54

• Manufacturer Part Number: AD9549/PCBZ
• Description: BOARD EVALUATION FOR AD9549
• Manufacturer: Analog Devices Inc

Specifications of AD9549/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9549
• Primary Attributes: 2 Inputs, 2 Outputs, VCO
• Secondary Attributes: CMOS, HSTL Output Logic, Graphical User Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9549
Register 0x0011—Reserved
Register 0x0012—Reset (Autoclear)
To reset the entire chip, the user can also use the (nonself-clearing) soft reset bit in Register 0x0000. Except for IRQ reset, the user normally
would not need to use this bit. However, if the user attempts to lock the loop for the first time when no signal is present, the user should
write 1 to Bits[4:0] of this register before attempting to lock the loop again.
Table 18.
Bits
7
6
5
4
3
2
1
0
Register 0x0013—Reset (Continued) (Not Autoclear)
Table 19.
Bits
7
3
2
1
0
SYSTEM CLOCK (REGISTER 0x0020 TO REGISTER 0x0023)
Register 0x0020—N-Divider
Table 20.
Bits
[4:0]
Register 0x0021—Reserved
Register 0x0022—PLL Parameters
Table 21.
Bits
7
[6:4]
3
2
[1:0]
Bit Name
History reset
Reserved
IRQ reset
FPFD reset
CPFD reset
LF reset
CCI reset
DDS reset
Bit Name
PD fund DDS
S-div/2 reset
R-div/2 reset
S-divider reset
R-divider reset
Bit Name
N-divider
Bit Name
VCO auto range
Reserved
2× reference
VCO range
Charge pump current
Description
Setting this bit clears the FTW monitor and pipeline.
Reserved.
Clear IRQ signal and IRQ status monitor.
Fine phase frequency detector reset.
Coarse phase frequency detector reset.
Loop filter reset.
Cascaded comb integrator reset.
Direct digital synthesis reset.
Description
Setting this bit powers down the DDS fundamental output but does not power down the spurs. It is used
during tuning of the spur killer circuit.
Asynchronous reset for S prescaler.
Asynchronous reset for R prescaler.
Synchronous (to S-divider prescaler output) reset for integer divider.
Synchronous (to R-divider prescaler output) reset for integer divider.
Description
These bits set the feedback divider for system clock PLL. There is a fixed/2 preceding this block, as well as
an offset of 2 added to this value. Therefore, setting this register to 00000 translates to an overall feedback
divider ratio of 4. See Figure 43.
Description
Automatic VCO range selection. Enabling this bit allows Bit 2 of this register to be set automatically.
Reserved
Enables a frequency doubler prior to the SYSCLK PLL and can be useful in reducing jitter induced by the
SYSCLK PLL. See Figure 42.
Select low range or high range VCO.
0 = low range (700 MHz to 810 MHz).
1 = high range (900 MHz to 1000 MHz). For system clock settings between 810 MHz and 900 MHz, use the
VCO Auto Range (Bit 7) to set the correct VCO range automatically.
Charge pump current.
00 = 250 μA.
01 = 375 μA.
10 = off.
11= 125 μA.
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