HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 106

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 13: DDR SDRAM
DDR SDRAM Connections
106
All DDR SDRAM interface signals are terminated.
The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best
access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when
using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller
IP core documentation is also available from within the EDK 8.1i development software
(see
Table 13-1
Table 13-1: FPGA-to-DDR SDRAM Connections
Category
“Related Resources,” page
shows the connections between the FPGA and the DDR SDRAM.
DDR SDRAM
Signal Name
SD_A12
SD_A11
SD_A10
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD_A3
SD_A2
SD_A1
SD_A0
www.xilinx.com
109).
FPGA Pin
Number
N5
N4
H2
H1
H3
H4
P2
T2
P1
R2
R3
T1
F4
Spartan-3E FPGA Starter Kit Board User Guide
Address inputs
UG230 (v1.2) January 20, 2011
Function
R