HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 79

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Analog to Digital Converter (ADC)
Spartan-3E FPGA Starter Kit Board User Guide
UG230 (v1.2) January 20, 2011
UCF Location Constraints
Interface
SPI Control Interface
R
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
Figure 10-5
including the I/O pin assignment and I/O standard used.
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.
Table 10-3
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 10-3: ADC Interface Signals
Figure 10-6
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s
complement binary value.
SPI_SCK
AD_CONV
SPI_MISO
Signal
NET
NET
NET
NET
NET
"SPI_MOSI"
"AMP_CS"
"SPI_SCK"
"AMP_SHDN"
"AMP_DOUT"
lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
provides the User Constraint File (UCF) constraints for the amplifier interface,
provides an example SPI bus transaction to the ADC.
Figure 10-5: UCF Location Constraints for the DAC Interface
FPGA Pin
N10
U16
P11
LOC
LOC
LOC
LOC
LOC
= "T4"
= "N7"
= "U16" |
= "P7"
= "E18" |
FPGAADC Clock
FPGAADC Active-High shutdown and reset.
FPGAADC Serial data: Master Input, Serial Output. Presents
www.xilinx.com
Direction
|
|
|
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
IOSTANDARD
the digital representation of the sample analog
values as two 14-bit two’s complement binary
values.
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 |
= LVCMOS33 ;
Analog to Digital Converter (ADC)
Description
SLEW
SLEW
SLEW
SLEW
= SLOW |
= SLOW |
= SLOW |
= SLOW |
DRIVE
DRIVE
DRIVE
DRIVE
= 6 ;
= 6 ;
= 8 ;
= 6 ;
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