HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 78

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 10: Analog Capture Circuit
78
AMP_DOUT
(from AMP)
(from FPGA)
SPI_MOSI
SPI_SCK
AMP_CS
SPI Control Interface
Previous 7
30
7
Figure 10-4: SPI Timing When Communicating with Amplifier
Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued)
Figure 10-3
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
Gain
-100
-10
-20
-50
-5
30
highlights the SPI-based communications interface with the amplifier. The gain
6
All timing is minimum in nanoseconds unless otherwise noted.
Spartan-3E
Master
FPGA
6
A3
B3
0
0
0
0
0
Figure 10-3: SPI Serial Interface to Amplifier
85 max
www.xilinx.com
5
AMP_DOUT
SPI_MOSI
AMP_CS
SPI_SCK
A2
B2
0
1
1
1
1
5
50
4
0
A
0
A1
B1
Spartan-3E FPGA Starter Kit Board User Guide
1
0
0
1
1
A
A Gain
1
4
Slave: LTC2624-1
A
2
A
3
3
A0
B0
1
0
1
0
1
B
0
50
UG230 (v1.2) January 20, 2011
B Gain
B
3
1
UG230_c10_03_030306
Minimum
B
Input Voltage Range
1.5875
1.6375
2
1.525
1.625
1.4
B
2
7
3
Figure
UG230_c10_04_022306
2
Maximum
10-4). The
1.7125
1.6625
1.775
1.675
1.9
R