HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 58

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 6: VGA Display Port
VGA Signal Timing
58
As shown in
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.
The signal timings in
25 MHz pixel clock and 60 Hz ± 1 refresh.
the timing symbols. The timing for the sync pulse width (T
intervals (T
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 6-2: 640x480 Mode VGA Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
Symbol
T
T
T
T
T
DISP
PW
FP
BP
S
FP
Sync pulse time
Display time
Pulse width
Front porch
Back porch
Figure
and T
Parameter
T
6-2, the VGA controller generates the horizontal sync (HS) and vertical
BP
pw
Table 6-2
) are based on observations from various VGA displays. The front
www.xilinx.com
Figure 6-3: VGA Control Timing
are derived for a 640-pixel by 480-row display using a
15.36 ms
16.7 ms
320 µs
928 µs
Time
64 µs
T
S
Vertical Sync
T
disp
Figure 6-3
Clocks
416,800
384,000
23,200
1,600
8,000
Spartan-3E FPGA Starter Kit Board User Guide
shows the relation between each of
Lines
521
480
10
29
2
PW
UG230 (v1.2) January 20, 2011
) and front and back porch
25.6 µs
3.84 µs
1.92 µs
640 ns
Time
32 µs
Horizontal Sync
UG230_c6_03_021706
T
fp
Clocks
800
640
T
96
16
48
bp
R