HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 84

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HW-SPAR3E-SK-US-G

Manufacturer Part Number
HW-SPAR3E-SK-US-G
Description
KIT STARTER SPARTAN-3E
Manufacturer
Xilinx Inc
Datasheets

Specifications of HW-SPAR3E-SK-US-G

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1507
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
StrataFlash Connections
84
Table 11-1
Although the XC3S500E FPGA only requires just slightly over 2 Mbits per configuration
image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit
StrataFlash. The Spartan-3E FPGA Starter Kit board ships with a 128 Mbit device. Address
line SF_A24 is not used.
In general, the StrataFlash device connects to the XC3S500E to support Byte Peripheral
Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not
connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins
during configuration. As described in
StrataFlash connections are shared with other components on the board.
Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
Stores non-volatile data from the FPGA.
shows the connections between the FPGA and the StrataFlash device.
www.xilinx.com
Table 11-1
Spartan-3E FPGA Starter Kit Board User Guide
and
Shared
Connections, some of the
UG230 (v1.2) January 20, 2011
R

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