HW-SPAR3E-SK-US-G Xilinx Inc, HW-SPAR3E-SK-US-G Datasheet - Page 108

• Manufacturer Part Number: HW-SPAR3E-SK-US-G
• Description: KIT STARTER SPARTAN-3E
• Manufacturer: Xilinx Inc

Specifications of HW-SPAR3E-SK-US-G

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1507

Chapter 13: DDR SDRAM
UCF Location Constraints
108
Address
Data
Figure 13-2
address pins, including the I/O pin assignment and the I/O standard used.
Figure 13-3
pins, including the I/O pin assignment and I/O standard used.
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Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs
"SD_A<12>"
"SD_A<11>"
"SD_A<10>"
"SD_A<9>"
"SD_A<8>"
"SD_A<7>"
"SD_A<6>"
"SD_A<5>"
"SD_A<4>"
"SD_A<3>"
"SD_A<2>"
"SD_A<1>"
"SD_A<0>"
Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os
"SD_DQ<15>"
"SD_DQ<14>"
"SD_DQ<13>"
"SD_DQ<12>"
"SD_DQ<11>"
"SD_DQ<10>"
"SD_DQ<9>"
"SD_DQ<8>"
"SD_DQ<7>"
"SD_DQ<6>"
"SD_DQ<5>"
"SD_DQ<4>"
"SD_DQ<3>"
"SD_DQ<2>"
"SD_DQ<1>"
"SD_DQ<0>"
provides the User Constraint File (UCF) constraints for the DDR SDRAM
provides the User Constraint File (UCF) constraints for the DDR SDRAM data
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www.xilinx.com
= "P2" |
= "N5" |
= "T2" |
= "N4" |
= "H2" |
= "H1" |
= "H3" |
= "H4" |
= "F4" |
= "P1" |
= "R2" |
= "R3" |
= "T1" |
= "H5" |
= "H6" |
= "G5" |
= "G6" |
= "F2" |
= "F1" |
= "E1" |
= "E2" |
= "M6" |
= "M5" |
= "M4" |
= "M3" |
= "L4" |
= "L3" |
= "L1" |
= "L2" |
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Spartan-3E FPGA Starter Kit Board User Guide
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UG230 (v1.2) January 20, 2011
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