PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 252

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
19.3.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
2.
3.
FIGURE 19-8:
TABLE 19-7:
DS39635C-page 252
INTCON
PIR3
PIE3
IPR3
RCSTA2
RCREG2 AUSART2 Receive Register
TXSTA2
SPBRG2
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Name
Note:
Initialize the SPBRG2 register for the appropriate
baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
Ensure bits, CREN and SREN, are clear.
RX2/DT2 Pin
TX2/CK2 Pin
(Interrupt)
CREN bit
RC2IF bit
RCREG2
bit SREN
SREN bit
Write to
Read
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
AUSART SYNCHRONOUS
MASTER RECEPTION
AUSART2 Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
Q2
CSRC
SPEN
Bit 7
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Bit 6
RX9
TX9
—
—
—
bit 0
TMR0IE
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
bit 2
INT0IE
CREN
TX2IF
TX2IE
TX2IP
SYNC
Bit 4
bit 3
ADDEN
RBIE
Bit 3
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
—
—
—
—
If interrupts are desired, set enable bit, RC2IE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RC2IF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RC2IE, was set.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG2 register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR0IF
BRGH
FERR
Bit 2
—
—
—
bit 5
INT0IF
OERR
TRMT
bit 6
Bit 1
 2010 Microchip Technology Inc.
—
—
—
CCP3IF
CCP3IE
CCP3IP
bit 7
RX9D
TX9D
RBIF
Bit 0
Q1 Q2 Q3 Q4
on Page
Values
Reset
63
65
65
65
66
66
66
66
‘0’