PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 43

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.8
When PRI_IDLE mode is selected, the designated
primary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin, if used by the oscillator) will stop oscillating.
In
SEC_IDLE), the Timer1 oscillator is operating and
providing the device clock. The Timer1 oscillator may
also run in all power-managed modes if required to
clock Timer1 or Timer3.
In internal oscillator modes (RC_RUN and RC_IDLE),
the internal oscillator block provides the device clock
source. The 31 kHz INTRC output can be used directly
to provide the clock and may be enabled to support var-
ious special features, regardless of the power-managed
mode (see Section 24.2 “Watchdog Timer (WDT)”
through Section 24.4 “Fail-Safe Clock Monitor” for
more information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up). The INTOSC output at 8 MHz may
be used directly to clock the device, or may be divided
down by the postscaler. The INTOSC output is disabled
if the clock is provided directly from the INTRC output.
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTRC is required to support WDT operation. The
Timer1 oscillator may be operating to support a
real-time clock. Other features may be operating that
do not require a device clock source (i.e., MSSP slave,
PSP, INTx pins and others). Peripherals that may add
significant
Section 27.2
Supply Current”.
TABLE 3-3:
 2010 Microchip Technology Inc.
RC, INTIO1
RCIO, INTIO2
ECIO
EC
LP, XT and HS
Note 1:
secondary
Oscillator Mode
Effects of Power-Managed Modes
on the Various Clock Sources
See
current
“DC Characteristics: Power-Down and
Table 5-2
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
clock
consumption
in
modes
Section 5.0 “Reset”
Floating, external resistor should pull high
Floating, external resistor should pull high
Floating, pulled by external clock
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
(SEC_RUN
are
listed
PIC18F6310/6410/8310/8410
OSC1 Pin
for time-outs due to Sleep and MCLR Reset.
and
in
3.9
Power-up delays are controlled by two timers, so that no
external Reset circuitry is required for most applications.
The delays ensure that the device is kept in Reset until
the device power supply is stable under normal
circumstances and the primary clock is operating and
stable. For additional information on power-up delays,
see
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up (Parameter 33,
Table
PWRTEN Configuration bit.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (LP, XT and HS modes). The
OST does this by counting 1024 oscillator cycles
before allowing the oscillator to clock the device.
When the HSPLL Oscillator mode is selected, the
device is kept in Reset for an additional 2 ms, following
the HS mode OST delay, so the PLL can lock to the
incoming clock frequency.
There is a delay of interval, T
Table
becomes ready to execute instructions. This delay runs
concurrently with any other delays. This may be the
only delay that occurs when any of the EC, RC or INTIO
modes are used as the primary clock source.
Section 5.5 “Device Reset
27-12). It is enabled by clearing (= 0) the
27-12), following POR while the controller
Power-up Delays
(1)
At logic low (clock/4 output)
Configured as PORTA, bit 6
Configured as PORTA, bit 6
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
OSC2 Pin
Timers”.
CSD
DS39635C-page 43
(Parameter 38,