PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 80

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6310/6410/8310/8410
TABLE 6-3:
DS39635C-page 80
TMR0H
TMR0L
T0CON
OSCCON
HLVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
CCPR3H
CCPR3L
CCP3CON
CVRCON
CMCON
TMR3H
TMR3L
T3CON
PSPCON
Legend:
Note
File Name
1:
2:
3:
4:
5:
6:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded locations are unimplemented, read as ‘0’.
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset
These registers and/or bits are not implemented on 64-pin devices, read as ‘0’.
The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as ‘0’. See
INTOSC
The RG5 bit is only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 reads as ‘0’. This bit is
read-only.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
STKFUL and STKUNF bits are cleared by user software or by a POR.
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Capture/Compare/PWM Register 2 High Byte
Capture/Compare/PWM Register 2 Low Byte
Capture/Compare/PWM Register 3 High Byte
Capture/Compare/PWM Register 3 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
VDIRMAG
TMR0ON
CVREN
C2OUT
IDLEN
WCOL
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
IBF
—
—
—
—
—
—
—
REGISTER FILE SUMMARY (PIC18F6310/6410/8310/8410) (CONTINUED)
Modes”.
SBOREN
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
ACKSTAT
T3CCP2
CVROE
SSPOV
C1OUT
T08BIT
T1RUN
IRCF2
Bit 6
CKE
OBF
—
—
—
—
—
—
—
—
(1)
2
C™ Slave Mode. MSSP Baud Rate Reload Register in I
T1CKPS1
T3CKPS1
SSPEN
ACKDT
VCFG1
ACQT2
DC1B1
DC2B1
DC3B1
IRCF1
IRVST
CVRR
C2INV
CHS3
T0CS
IBOV
(BOR)”.
Bit 5
D/A
—
—
PSPMODE
T1CKPS0
T3CKPS0
HLVDEN
ACKEN
CVRSS
VCFG0
ACQT1
DC1B0
DC2B0
DC3B0
C1INV
IRCF0
CHS2
T0SE
Bit 4
CKP
—
RI
P
T1OSCEN
CCP1M3
CCP2M3
CCP3M3
HLVDL3
T3CCP1
SSPM3
PCFG3
ACQT0
RCEN
OSTS
CHS1
CVR3
Bit 3
PSA
CIS
TO
—
—
S
TMR2ON
CCP1M2
CCP2M2
CCP3M2
T1SYNC
T3SYNC
HLVDL2
SSPM2
PCFG2
ADCS2
T0PS2
CHS0
CVR2
IOFS
Bit 2
CM2
R/W
PEN
PD
—
—
2
GO/DONE
T2CKPS1
TMR1CS
TMR3CS
C Master Mode.
CCP1M1
CCP2M1
CCP3M1
HLVDL1
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
CVR1
SCS1
Bit 1
POR
CM1
UA
—
—
 2010 Microchip Technology Inc.
SWDTEN
T2CKPS0
TMR1ON
TMR3ON
CCP1M0
CCP2M0
CCP3M0
HLVDL0
SSPM0
PCFG0
ADCS0
T0PS0
ADON
SCS0
CVR0
Bit 0
BOR
CM0
SEN
BF
—
0000 0000
xxxx xxxx
1111 1111
0100 q000
0-00 0101
---- ---0
0q-1 11q0
xxxx xxxx
0000 0000
0000 0000
1111 1111
-000 0000
-000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
--00 0000
--00 qqqq
0-00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 0000
--00 0000
xxxx xxxx
0000 0000
--00 0000
0000 0000
0000 0111
0000 0000
0000 0000
0000 0000
0000 ----
POR, BOR
Section 3.6.4 “PLL in
Value on
on page:
64, 178,
64, 178,
64, 179,
Details
64, 153
64, 153
64, 151
64, 275
64, 291
64, 159
64, 159
64, 155
64, 162
64, 162
64, 161
64, 186
64, 189
64, 264
64, 264
64, 255
64, 256
64, 257
65, 168
65, 168
65, 167
65, 168
65, 168
65, 167
65, 168
65, 168
65, 167
65, 271
65, 265
65, 163
65, 165
65, 163
65, 149
56, 64,
42, 64
123
186
188
179