PIC18LF6310-I/PT Microchip Technology, PIC18LF6310-I/PT Datasheet - Page 407

• Manufacturer Part Number: PIC18LF6310-I/PT
• Description: IC PIC MCU FLASH 4KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF6310-I/PT

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 54
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• No. Of Pwm: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer0 .............................................................................. 151
Timer1 .............................................................................. 155
Timer2 .............................................................................. 161
Timer3 .............................................................................. 163
Timing Diagrams
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16-Bit Mode Timer Reads and Writes ...................... 152
Associated Registers ............................................... 153
Clock Source Edge Select (T0SE Bit) ...................... 152
Clock Source Select (T0CS Bit) ............................... 152
Operation ................................................................. 152
Overflow Interrupt .................................................... 153
Prescaler. See Prescaler, Timer0.
16-Bit Read/Write Mode ........................................... 157
Associated Registers ............................................... 159
Interrupt .................................................................... 158
Low-Power Option ................................................... 157
Operation ................................................................. 156
Oscillator .......................................................... 155, 157
Oscillator Layout Considerations ............................. 158
Overflow Interrupt .................................................... 155
Resetting, Using a Special Event Trigger
TMR1H Register ...................................................... 155
TMR1L Register ....................................................... 155
Use as a Real-Time Clock ....................................... 158
Using as a Clock Source .......................................... 157
Associated Registers ............................................... 162
Interrupt .................................................................... 162
Operation ................................................................. 161
Output ...................................................................... 162
PR2 Register ............................................................ 173
TMR2 to PR2 Match Interrupt .................................. 173
16-Bit Read/Write Mode ........................................... 165
Associated Registers ............................................... 165
Operation ................................................................. 164
Oscillator .......................................................... 163, 165
Overflow Interrupt ............................................ 163, 165
Special Event Trigger (CCP) .................................... 165
TMR3H Register ...................................................... 163
TMR3L Register ....................................................... 163
A/D Conversion ........................................................ 388
Acknowledge Sequence .......................................... 210
Asynchronous Reception ................................. 230, 249
Asynchronous Transmission ............................ 227, 247
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 225
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 233
Baud Rate Generator with Clock Arbitration ............ 204
BRG Overflow Sequence ......................................... 225
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 375
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Start
Bus Collision During a Stop Condition (Case 1) ...... 215
Bus Collision During a Stop Condition (Case 2) ...... 215
Output (CCP) ................................................... 158
(Back to Back) ......................................... 227, 247
Normal Operation ............................................ 233
Start Condition ................................................. 213
Condition (Case 1) ........................................... 214
Condition (Case 2) ........................................... 214
Condition (SCL = 0) ......................................... 213
Condition (SDA Only) ...................................... 212
PIC18F6310/6410/8310/8410
Bus Collision for Transmit and Acknowledge .......... 211
Capture/Compare/PWM (All CCP Modules) ............ 377
CLKO and I/O .......................................................... 372
Clock Synchronization ............................................. 197
Clock/Instruction Cycle .............................................. 73
Example SPI Master Mode (CKE = 0) ..................... 378
Example SPI Master Mode (CKE = 1) ..................... 379
Example SPI Slave Mode (CKE = 0) ....................... 380
Example SPI Slave Mode (CKE = 1) ....................... 381
External Clock (All Modes Except PLL) ................... 370
External Memory Bus for SLEEP (16-Bit
External Memory Bus for SLEEP (8-Bit
External Memory Bus for TBLRD (16-Bit
External Memory Bus for TBLRD (16-Bit
External Memory Bus for TBLRD (8-Bit
External Memory Bus for TBLRD (8-Bit
Fail-Safe Clock Monitor ........................................... 294
High/Low-Voltage Detect (VDIRMAG = 1) ............... 278
High/Low-Voltage Detect Characteristics ................ 367
High/Low-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
Master SSP I
Master SSP I
Parallel Slave Port (PSP) Read ............................... 150
Parallel Slave Port (PSP) Write ............................... 149
Program Memory Read ........................................... 373
Program Memory Write ........................................... 374
PWM Output ............................................................ 173
Repeated Start Condition ........................................ 206
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 234
Slave Synchronization ............................................. 183
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ........................................ 182
SPI Mode (Slave Mode, CKE = 0) ........................... 184
SPI Mode (Slave Mode, CKE = 1) ........................... 184
Synchronous Reception (Master Mode,
Synchronous Transmission ............................. 235, 250
Synchronous Transmission
Time-out Sequence on POR w/PLL Enabled
2
2
2
2
2
2
2
2
2
2
2
2
2
C Bus Data ............................................................ 382
C Bus Start/Stop Bits ............................................ 382
C Master Mode (7 or 10-Bit Transmission) ........... 208
C Master Mode (7-Bit Reception) ......................... 209
C Master Mode First Start Bit ................................ 205
C Slave Mode (10-Bit Reception, SEN = 0) .......... 194
C Slave Mode (10-Bit Reception, SEN = 1) .......... 199
C Slave Mode (10-Bit Transmission) .................... 195
C Slave Mode (7-bit Reception, SEN = 0) ............ 192
C Slave Mode (7-Bit Reception, SEN = 1) ............ 198
C Slave Mode (7-Bit Transmission) ...................... 193
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 210
Microprocessor Mode) ..................................... 101
Microprocessor Mode) ..................................... 104
Extended Microcontroller Mode) ...................... 100
Microprocessor Mode) ..................................... 100
Extended Microcontroller Mode) ...................... 103
Microprocessor Mode) ..................................... 103
(VDIRMAG = 0) ............................................... 277
Sequence (7 or 10-Bit Address Mode) ............ 200
Timer (OST) and Power-up Timer (PWRT) ..... 375
V
SREN) ..................................................... 237, 252
(Through TXEN) ...................................... 236, 251
(MCLR Tied to V
DD
Rise > T
2
2
C Bus Data ....................................... 384
C Bus Start/Stop Bits ........................ 384
PWRT
DD
) ............................................ 61
) .......................................... 61
DD
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