AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 109

• Manufacturer Part Number: AT89C51IC2-RLTIL
• Description: IC 8051 MCU FLASH 32K 44VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51IC2-RLTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Default Values
Software Registers
4301D–8051–02/08
Table 85. Program Lock Bits
Note:
These security bits protect the code access through the parallel programming interface.
They are set by default to level 4. The code access through the ISP is still possible and
is controlled by the "software security bits" which are stored in the extra Flash memory
accessed by the ISP firmware.
To load a new application with the parallel programmer, a chip erase must first be done.
This will set the HSB in its inactive state and will erase the Flash memory. The part ref-
erence can always be read using Flash parallel programming modes.
The default value of the HSB provides parts ready to be programmed with ISP:
•
•
•
•
Several registers are used, in factory and by parallel programmers, to make copies of
hardware registers contents. These values are used by Atmel ISP.
These registers are in the "Extra Flash Memory" part of the Flash memory. This block is
also called "XAF" or eXtra Array Flash. They are accessed in the following ways:
•
•
•
Several software registers are described in Table 86.
Security
Level
BLJB: Programmed force ISP operation.
X2: Unprogrammed to force X1 mode (Standard Mode).
XRAM: Unprogrammed to valid XRAM
LB2-0: Security level four to protect the code from a parallel access with maximum
security.
Commands issued by the parallel memory programmer.
Commands issued by the ISP software.
Calls of API issued by the application software.
1
2
3
4
Program Lock Bits
U: unprogrammed or "one" level.
P: programmed or "zero" level.
X: don’t care
WARNING: Security level ‘2’ and ‘3‘ should only be programmed after Flash and code
verification.
LB0
U
P
X
X
LB1
U
U
P
X
LB2
U
U
U
P
Protection Description
No program lock features enabled.
MOVC instruction executed from external program memory is disabled
from fetching code Bytes from internal memory, EA is sampled and
latched on reset, and further parallel programming of the Flash is
disabled. ISP and software programming with API are still allowed.
Same as 2, also verify through parallel programming interface is
disabled.
Same as 3, also external execution is disabled. (Default)
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