AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 88

• Manufacturer Part Number: AT89C51IC2-RLTIL
• Description: IC 8051 MCU FLASH 32K 44VQFP
• Manufacturer: Atmel
• Series: 89Cr

Specifications of AT89C51IC2-RLTIL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Slave Receiver Mode
Slave Transmitter Mode
88
AT89C51IC2
When the slave address and the direction bit have been transmitted and an acknowl-
edgement bit has been received, the serial interrupt flag is set again and a number of
status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and
also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1). The appropriate
action to be taken for each of these status code is detailed in Table 69. This scheme is
repeated until a STOP condition is transmitted.
SSIE, CR2, CR1 and CR0 are not affected by the serial transfer and are referred to
Table 7 to Table 11. After a repeated START condition (state 10h) SSLC may switch to
the master transmitter mode by loading SSDAT with SLA+W.
In the slave receiver mode, a number of data bytes are received from a master transmit-
ter (Figure 40). To initiate the slave receiver mode, SSADR and SSCON must be loaded
as follows:
Table 65. SSADR: slave receiver mode initialization
The upper 7 bits are the address to which SSLC will respond when addressed by a mas-
ter. If the LSB (GC) is set SSLC will respond to the general call address (00h); otherwise
it ignores the general call address.
Table 66. SSCON: slave receiver mode initialization
CR0, CR1 and CR2 have no effect in the slave mode. SSIE must be set to enable
SSLC. The AA bit must be set to enable the own slave address or the general call
address acknowledgement. STA, STO and SI must be cleared.
When SSADR and SSCON have been initialised, SSLC waits until it is addressed by its
own slave address followed by the data direction bit which must be at logic 0 (W) for
SSLC to operate in the slave receiver mode. After its own slave address and the W bit
have been received, the serial interrupt flag is set and a valid status code can be read
from SSCS. This status code is used to vector to an interrupt service routine.The appro-
priate action to be taken for each of these status code is detailed in Table 70. The slave
receiver mode may also be entered if arbitration is lost while SSLC is in the master
mode (states 68h and 78h).
If the AA bit is reset during a transfer, SSLC will return a not acknowledge (logic 1) to
SDA after the next received data byte. While AA is reset, SSLC does not respond to its
own slave address. However, the 2-wire bus is still monitored and address recognition
may be resume at any time by setting AA. This means that the AA bit may be used to
temporarily isolate SSLC from the 2-wire bus.
In the slave transmitter mode, a number of data bytes are transmitted to a master
receiver (Figure 41). Data transfer is initialized as in the slave receiver mode. When
SSADR and SSCON have been initialized, SSLC waits until it is addressed by its own
bit rate
CR2
A6
SSIE
A5
1
STA
A4
0
own slave address
STO
A3
0
A2
SI
0
AA
A1
1
bit rate
CR1
A0
4301D–8051–02/08
bit rate
CR0
GC