AT89C51IC2-RLTIL Atmel, AT89C51IC2-RLTIL Datasheet - Page 48

IC 8051 MCU FLASH 32K 44VQFP

AT89C51IC2-RLTIL

Manufacturer Part Number
AT89C51IC2-RLTIL
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
89Cr
Datasheet

Specifications of AT89C51IC2-RLTIL

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
640
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
ATMEL
Quantity:
4 116
Part Number:
AT89C51IC2-RLTIL
Manufacturer:
Atmel
Quantity:
10 000
Automatic Address
Recognition
Given Address
48
AT89C51IC2
Figure 19. UART Timings in Modes 2 and 3
The automatic address recognition feature is enabled when the multiprocessor commu-
nication feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor
communication feature by allowing the serial port to examine the address of each
incoming command frame. Only when the serial port recognizes its own address, the
receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU
is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this
configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the
received command frame address matches the device’s address and is terminated by a
valid stop bit.
To support automatic address recognition, a device is identified by a given address and
a broadcast address.
Note:
Each device has an individual address that is specified in SADDR register; the SADEN
register is a mask byte that contains don’t-care bits (defined by zeros) to form the
device’s given address. The don’t-care bits provide the flexibility to address one or more
slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111
1111b.
For example:
The following is an example of how to use given addresses to address different slaves:
SMOD0=0
SMOD0=1
SMOD0=1
Slave A:SADDR1111 0001b
Slave B:SADDR1111 0011b
Slave C:SADDR1111 0010b
RXD
FE
RI
RI
The multiprocessor communication and automatic address recognition features cannot
be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).
SADDR0101 0110b
SADEN1111 1100b
Given0101 01XXb
SADEN1111 1010b
Given1111 0X0Xb
SADEN1111 1001b
Given1111 0XX1b
SADEN1111 1101b
Given1111 00X1b
Start
bit
D0
D1
D2
D3
Data byte
D4
D5
D6
D7
Ninth
D8
bit
Stop
bit
4301D–8051–02/08

Related parts for AT89C51IC2-RLTIL