DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 15

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

30. Module: SPI
31. Module: UART
© 2010 Microchip Technology Inc.
SPI1 functionality for pin 34 (U1RX/SDI1/RF2) is
enabled by the SPI2 module. As a result, two side
effects occur:
1. RF2 functionality is disabled if the SPI2 module
2. This pin will not function as SDI1 if the SPI1
This issue affects 64-pin devices only, including
the following devices:
• dsPIC33FJ64MC506
• dsPIC33FJ64MC706
• dsPIC33FJ128MC506
• dsPIC33FJ128MC706
Work around
Two conditions apply:
1. If the SPI2 module is used, pin 34 cannot be
2. If the SPI1 module is used, the SPI2 module
Affected Silicon Revisions
The auto-baud feature may miscalculate for
certain baud rate and clock speed combinations,
resulting in a BRG value that is greater than or less
than the expected value by 1. This may result in
reception or transmission failures.
Work around
Test the auto-baud rate at various clock speed and
baud rate combinations that would be used in an
application. If an inaccurate BRG value is
generated, manually correct the baud rate in the
user software.
Affected Silicon Revisions
A2
A2
X
X
is enabled.
module is enabled.
used as an I/O (RF2). Using another I/O pin is
recommended.
must also be enabled to gain SDI1 functionality
on pin 34. As an alternative, I/O (RF2) can be
configured as an input, which will allow pin 34
to function as SDI1.
A3
A3
X
X
A4
A4
X
X
32. Module: Device ID Register
On a few devices, the content of the Device ID
register can change from the factory programmed
default value immediately after RTSP or ICSP™
Flash programming.
As a result, development tools will not recognize
these devices and will generate an error message
indicating that the device ID and the device part
number
peripherals will be reconfigured and will not
function as described in the device data sheet.
Refer to Section 5. “Flash Programming”
(DS70191), of the “dsPIC33F Family Reference
Manual” for an explanation of RTSP and ICSP
Flash programming.
Work around
All RTSP and ICSP Flash programming routines
(excluding Configuration Memory programming
routines) must be modified as follows:
1. No word programming is allowed. Any word
2. During row programming, load write latches as
3. After latches are loaded, reload any latch
4. Start
5. After row programming is complete, verify the
6. If Flash verification errors are found, repeat
Steps 1 through 5 in the work around are
implemented in MPLAB IDE version 8.00 or higher
for the MPLAB ICD 2, MPLAB REAL ICE™ in-circuit
emulator and PM3 tools.
Affected Silicon Revisions
A2
X
programming must be replaced with row
programming.
described in 5.4.2.3 “Loading Write Latches”
of
(DS70191),
Reference Manual”.
location (in a given row) that has 5 LSB set to
0x18, with the original data. For example,
reload one of the following latch locations with
the desired data:
0xXXXX18, 0xXXXX38, 0xXXXX58,
0xXXXX78, 0xXXXX98, 0xXXXXB8,
0xXXXXD8, 0xXXXXF8
NVMOP<3:0> = ‘0001’ (memory row program
operation) in the NVMCON register.
contents of Flash memory.
steps 2 through 5. If Flash verification errors
are found after a second iteration, please
contact your local Microchip representative.
A3
Section
X
do
row
A4
X
not
of
5.
programming
match.
the
“Flash
“dsPIC33F
Additionally,
DS80447D-page 15
Programming”
by
Family
setting
some