DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 20

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

49. Module: I
50. Module: Internal Voltage Regulator
DS80447D-page 20
In 10-bit Addressing mode, some address
matches do not set the RBF flag or load the
receive register, I2CxRCV, if the lower address
byte
particular, these include all addresses with the
form XX0000XXXX and XX1111XXXX, with the
following exceptions:
• 001111000X
• 011111001X
• 101111010X
• 111111011X
Work around
Ensure that the lower address byte in 10-bit
Addressing mode does not match any 7-bit
reserved addresses.
Affected Silicon Revisions
When the VREGS bit (RCON<8>) is set to a logic
‘0’, the device may reset, and higher sleep current
may be observed.
Work around
Ensure that the VREGS bit (RCON<8>) is set to a
logic ‘1’ for device Sleep mode operation.
Affected Silicon Revisions
A2
A2
X
X
matches
A3
A3
X
X
2
C
A4
A4
X
X
the
reserved
addresses.
In
51. Module: PSV Operations
52. Module: UART
53. Module: UART
An address error trap occurs in certain addressing
modes when accessing the first four bytes of a
PSV page. This only occurs when using the
following addressing modes:
• MOV.D
• Register Indirect Addressing (Word or Byte
Work around
Do not perform PSV accesses to any of the first
four bytes using the above addressing modes. For
applications using the C language, MPLAB C
Compiler for dsPIC DSCs (formerly known as the
MPLAB C30 C Compiler), version 3.11 or higher,
provides the following command-line switch that
implements a work around for the erratum.
-merrata=psv_trap
Refer to the readme.txt file in the MPLAB C
Compiler for dsPIC DSCs, v3.11 tool suite for
further details.
Affected Silicon Revisions
The UART error interrupt may not occur, or may
occur at an incorrect time, if multiple errors occur
during a short period of time.
Work around
Read the error flags in the UxSTA register
whenever a byte is received to verify the error
status. In most cases, these bits will be correct,
even if the UART error interrupt fails to occur.
Affected Silicon Revisions
When the UART is operating in 8-bit mode
(PDSEL = 0x) and using the IrDA
decoder (IREN = 1), the module incorrectly
transmits a data payload of 80h as 00h.
Work around
None.
Affected Silicon Revisions
A2
A2
A2
mode) with pre/post-decrement
X
X
X
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
© 2010 Microchip Technology Inc.
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