DSPIC33FJ128MC510-I/PT Microchip Technology, DSPIC33FJ128MC510-I/PT Datasheet - Page 19

• Manufacturer Part Number: DSPIC33FJ128MC510-I/PT
• Description: IC DSPIC MCU/DSP 128K 100TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ128MC510-I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 24x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 2.75V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 85
• Flash Memory Size: 128KB
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1001 - DSPIC33 BREAKOUT BOARDAC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32DV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

43. Module: UART
44. Module: SPI
45. Module: I
© 2010 Microchip Technology Inc.
When the UART is configured for IR interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLK pin is present only when
the module is transmitting. The pin is idle at all
other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
Setting the DISSCK bit in the SPIxCON1 register
does not allow the user application to use the SCK
pin as a general purpose I/O pin.
Work around
None.
Affected Silicon Revisions
The BCL bit in I2CSTAT can be cleared only with
16-bit operation, and can be corrupted with 1-bit or
8-bit operations on I2CSTAT.
Work around
Use 16-bit operations to clear BCL.
Affected Silicon Revisions
A2
A2
A2
X
X
X
A3
A3
A3
X
X
X
2
C
A4
A4
A4
X
X
X
46. Module: I
47. Module: I
48. Module: I
If there are two I
them acts as the master receiver and the other
acts as the slave transmitter. If both devices are
configured for 10-bit Addressing mode, and have
the same value in the A10 and A9 bits of their
addresses: then, when the slave select address is
sent from the master, both the master and slave
acknowledge it. When the master sends out the
read operation, both the master and the slave
enter into Read mode, and both of them transmit
the data. The resultant data will be the ANDing of
the two transmissions.
Work around
In all I
A10 and A9, should be different.
Affected Silicon Revisions
When the I
slave with an address of 0x102, the I2CxRCV
register content for the lower address byte is 0x01,
rather than 0x02. However, the I
acknowledges both address bytes.
Work around
None.
Affected Silicon Revisions
With the I
external interrupt input functions associated with
the SCL and SDA pins (if any) do not reflect the
actual digital logic levels on the pins.
Work around
If the SDA and/or SCL pins need to be polled,
these pins should be connected to other port pins
to be read correctly. This issue does not affect the
operation of the I
Affected Silicon Revisions
A2
A2
A2
X
X
X
2
C devices, the addresses, as well as bits
A3
A3
A3
X
X
X
2
C module enabled, the PORT bits and
2
2
2
2
C
C
C
C module is configured as a 10-bit
A4
A4
A4
X
X
X
2
2
C module.
C devices on the bus, one of
DS80447D-page 19
2
C module